At data rates of 25 Gbps and above (PCIe Gen4/Gen5, 100G/400G/800G Ethernet, 112G PAM4), the unused portion of a plated through-hole via acts as an unterminated stub — causing signal reflections that degrade the eye diagram and increase bit error rates. Back-drilling removes this stub from the opposite side of the board, leaving only the portion of the via that connects its target layers.
Back-Drill Process Parameters
Depth Control Accuracy
±0.05 mm — verified by post-drill inspection on every panel
Drill Diameter
Slightly larger than the original via hole to ensure complete stub removal
Drill Direction
From the opposite side of the board, stopping a controlled distance from the target signal layer
Design Rule
Leave clearance between back-drill holes and adjacent traces to account for the larger drill diameter
High-speed serial links — PCIe, Ethernet, NVLink, DDR memory buses — rely on tightly controlled differential impedance to maintain signal integrity. We model every controlled-impedance stackup in Polar Instruments software before fabrication, adjusting trace width, dielectric thickness, and material Dk to hit the target impedance. TDR (Time Domain Reflectometry) test coupons on every production panel verify the result.
Target Impedances
85Ω (PCIe, DDR) and 100Ω (Ethernet, high-speed differential)
Standard Tolerance
±5%
Critical Tolerance
±3% — available for designs requiring tighter control
Verification
TDR impedance coupon on every production panel
SI Support
Full-link simulation and stackup modeling during DFM review
High-Layer-Count Capability — 20 to 68 Layers
Data center switches, AI training backplanes, and 800G switch fabrics demand layer counts far beyond standard multilayer PCBs. The increased layer count is driven by the need for multiple high-speed routing layers, dedicated ground references for every signal layer, multiple split power planes, and shielding layers between high-speed regions.
Layer Range
20–68 layers for high-speed digital applications
Aspect Ratio
Up to 20:1 on thick high-layer-count boards
Material
Ultra-low-loss laminates throughout — no FR-4 downgrade on inner layers
Registration
Layer-to-layer within ±0.05 mm — X-ray verified on every panel
Warpage Control
Symmetrical stackup with low-CTE cores — flatness verified before drilling
