HMC705LP4E
Brand: ADI
The HMC705LP4E is a low noise GaAs HBT programmable frequency divider from Analog Devices, capable of dividing any input frequency from 100 MHz to 6.5 GHz by any integer value from N=1 to N=17. With an ultra-low SSB phase noise floor of -153 dBc/Hz at 100 kHz offset, this prescaler enables high-performance, fast-settling PLL frequency synthesizer architectures used in radar, satcom, test equipment, and electronic warfare systems. The flexible single-ended or differential I/O, 5-bit parallel programming interface, and compact 4x4mm 24-QFN package make it a versatile building block for precision LO generation and clock distribution chains.
Product Specifications
HMC705LP4E - ADI GaAs HBT Programmable Frequency Divider, N=1-17, 6.5GHz
Analog Devices Inc. - Low Noise GaAs HBT Prescaler, -153 dBc/Hz SSB Phase Noise Floor, 24-QFN 4x4mm
MFR Part #: HMC705LP4ESuperb SKU: SUP-HMC705LP4E
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The HMC705LP4E is a low noise GaAs HBT programmable frequency divider from Analog Devices, capable of dividing any input frequency from 100 MHz to 6.5 GHz by any integer value from N=1 to N=17. With an ultra-low SSB phase noise floor of -153 dBc/Hz at 100 kHz offset, this prescaler enables high-performance, fast-settling PLL frequency synthesizer architectures used in radar, satcom, test equipment, and electronic warfare systems. The flexible single-ended or differential I/O, 5-bit parallel programming interface, and compact 4x4mm 24-QFN package make it a versatile building block for precision LO generation and clock distribution chains.
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Key Performance Highlights
Technology
GaAs HBT
Division Range
N = 1 to 17
Max Input Frequency
6.5 GHz
SSB Phase Noise Floor
-153 dBc/Hz @ 100kHz
Output Type
Single-ended / Differential
Package
24-QFN (4 x 4 mm)
Technical Specifications
| Manufacturer | Analog Devices Inc. (formerly Hittite Microwave) |
| Part Number | HMC705LP4E |
| Device Type | Programmable Frequency Divider / Prescaler |
| Technology | GaAs HBT (Gallium Arsenide Heterojunction Bipolar Transistor) |
| Division Ratio (N) | N = 1 to 17 (integer, programmable via 5-bit parallel) |
| Input Frequency Range | 100 MHz to 6.5 GHz |
| SSB Phase Noise Floor | -153 dBc/Hz at 100 kHz offset |
| Input Interface | Differential (can be driven single-ended with AC termination) |
| Output Interface | Single-ended or differential (programmable) |
| Programming Interface | 5-bit parallel (D0-D4) - set N value in binary |
| Supply Voltage | 5.0 V nominal (4.75V to 5.25V operating range) |
| Operating Temperature | -40C to +85C |
| Package | 24-QFN (4 mm x 4 mm), leadless SMD |
| Mounting | Surface Mount (SMT) - expose pad for thermal/ground |
| RoHS | RoHS Compliant |
Product Details
Programmable Divider Architecture
The HMC705LP4E uses advanced GaAs HBT technology to achieve low-noise, high-frequency division. The programmable N=1-17 range is set via 5 parallel control pins (D0-D4) using binary coding — from 00000 (N=1, pass-through) to 10001 (N=17). This digital control enables dynamic frequency planning in PLL synthesizers without changing hardware.
Ultra-Low Phase Noise: The -153 dBc/Hz SSB phase noise floor at 100 kHz offset is critical for high-performance PLLs. The divider's noise contribution directly impacts the PLL's in-band phase noise — a lower divider noise floor translates to cleaner synthesizer output across the loop bandwidth.
Flexible I/O: The differential input can be driven single-ended by AC-coupling the unused port to ground through 50 ohms. Output can be taken single-ended or differentially, matching common ADC/DAC clock and PLL phase-frequency detector (PFD) input requirements.
Key Applications
PLL Frequency Synthesizers - Fast-settling, low-noise fractional-N/integer-N PLLs
LO Generation Chains - Divide VCO output for multiple LO frequencies
Test & Measurement - Signal generators, phase noise analyzers, spectrum analyzers
Radar Systems - Coherent LO distribution, multi-channel phase synchronization
Satcom Equipment - Up/down-converter LO chains, frequency planning
Electronic Warfare - Fast-hopping synthesizers for jammers and SIGINT receivers
Clock Distribution - Divide master clock for multiple synchronized domains
Divide-by-N Programming Examples
| Input Freq (Fin) | N Value | Output Freq (Fout) | Typical Application |
|---|---|---|---|
| 6.0 GHz (VCO) | N = 2 | 3.0 GHz | S-band LO |
| 6.0 GHz (VCO) | N = 4 | 1.5 GHz | L-band reference |
| 5.8 GHz (VCO) | N = 8 | 725 MHz | PLL PFD comparison freq |
| 4.0 GHz (VCO) | N = 16 | 250 MHz | ADC sample clock |
| 3.4 GHz (VCO) | N = 17 | 200 MHz | Reference distribution |
Why Source HMC705LP4E from Superb Automation?
PLL Synthesizer BOM - HMC705LP4E + PFD + VCO + loop filter + reference oscillator - one PO
High-Frequency PCB Design - 6.5 GHz impedance-controlled traces, differential pair routing, low-loss substrate
QFN Soldering + Inspection - 4x4mm QFN reflow with X-ray for exposed pad void verification
PLL Loop Filter Design - We can assist with passive/active loop filter component selection and layout
25 Years Trusted - Electronic components + PCBA partner since 2000
Genuine Parts - Direct from authorized ADI channels, full lot traceability
Frequently Asked Questions
What is the HMC705LP4E used for?
The HMC705LP4E is a GaAs HBT programmable frequency divider for PLL synthesizers, LO generation, and clock distribution. It divides any 100MHz-6.5GHz input by N=1-17 with -153 dBc/Hz SSB phase noise. Common in radar, satcom, test equipment, and fast-hopping military systems.
How do I program the division ratio?
Program N via 5 parallel pins D0-D4 in binary: 00000 = N=1, 00001 = N=2, ..., 10001 = N=17. Connect D0-D4 to a microcontroller, FPGA, or DIP switch. Values 10010 to 11111 (18-31) are reserved — do not use. N=1 passes signal through without division.
Can I use single-ended input with HMC705LP4E?
Yes. The differential input can be driven single-ended by AC-coupling the unused input port to ground through a 50-ohm resistor. Use a DC-blocking capacitor (100pF typical) on the active input. Output can similarly be taken single-ended or differentially.
What is the phase noise contribution to a PLL?
The divider's phase noise is multiplied by 20log(N) inside the PLL loop. With a -153 dBc/Hz noise floor, the HMC705LP4E adds minimal noise. For example, at N=17 the divider contributes only -153 + 20log(17) = -153 + 24.6 = -128.4 dBc/Hz to the PLL output — excellent for high-performance synthesizers.
What supply voltage does HMC705LP4E need?
Single 5.0V supply (4.75V-5.25V range). Use a low-noise LDO for the supply rail — power supply noise can modulate the divider and degrade phase noise. Add 100pF + 0.1uF + 10uF decoupling capacitors close to the Vcc pin. Connect exposed pad to ground plane for thermal and RF performance.
