NVIDIA's NVLink Domain architecture extends GPU-to-GPU connectivity beyond a single baseboard, creating a unified 800 GB/s fabric across an entire rack of 72 GPUs. The interconnect backplane is the physical layer that makes this possible — a specialized PCB that routes thousands of differential pairs between GPU trays and NVSwitch trays. This article explores the design methodology behind these rack-scale PCBs.

NVLink Domain: Physical Architecture

In the GB200 NVL72 rack, NVLink Domain uses copper backplane interconnect rather than optical. The architecture comprises:

• Compute trays: Each holds 2 GB200 superchips (2 Grace CPUs + 4 Blackwell GPUs) — total 18 compute trays per rack

• NVSwitch trays: 9 NVSwitch trays, each with 2 NVSwitch chips, providing the non-blocking fabric

• Backplane: A massive passive copper backplane connecting all 18 compute trays to all 9 switch trays, achieving 130 TB/s aggregate bisection bandwidth

The backplane must route approximately 7,200 NVLink lanes at 200 GB/s per lane (100 GB/s per direction), totaling 1.8 PB/s of full-duplex bandwidth through copper traces.

Channel Design: 100G PAM4 Over Copper

Each NVLink 5 lane operates at 100 Gbps PAM4 (200 GT/s), meaning the Nyquist frequency is 50 GHz. At these frequencies, maintaining signal integrity over 12–18 inch backplane traces is extraordinarily challenging:

• Insertion loss: Megtron 7 at 50 GHz exhibits ~1.5 dB/in loss. A 15-inch trace accumulates 22.5 dB of loss before connector losses — requiring receive-side equalization (CTLE + DFE) with 30+ dB of compensation capability

• Return loss: Must remain below −15 dB across 10 MHz–50 GHz. Impedance discontinuities at connectors and vias are the primary contributors

• Skew: Intra-pair skew below 0.5 ps; inter-lane skew across the full NVLink bundle below 1 UI (5 ps at 200 GT/s)

Backplane Layer Stackup

A rack-scale NVLink backplane typically uses 28–36 layers:

• L1–L2: Top layer for connector footprints + GND plane

• L3–L16: 14 signal routing layers (NVLink pairs, organized by switch domain)

• L17–L20: Power distribution (48V bus, management power)

• L21–L34: 14 additional signal routing layers

• L35–L36: GND plane + Bottom connector layer

Critical design rule: Signal layers must be grouped by NVSwitch domain to minimize via transitions. Each NVSwitch tray connects to a specific set of compute trays — layer assignment maps 1:1 to this connectivity graph to avoid crossing routing planes unnecessarily.

Connector Technology

The backplane uses high-density orthogonal connectors rated for 112 Gbps PAM4:

• Pin count: Each connector carries 32–64 differential pairs in a compact footprint (~25 mm × 15 mm)

• Insertion force: Approximately 0.5N per pin × 200+ pins = 100N+ per connector — the backplane must be mechanically reinforced

• Wipe distance: 1.5 mm minimum to ensure reliable contact through thermal expansion and vibration

• Crosstalk: Connector-to-connector isolation >60 dB at 50 GHz achieved through integrated ground shields

Thermal Considerations

Though largely passive, the backplane dissipates significant power from trace I²R losses and connector contact resistance:

• Total trace current: At 0.8V signaling swing into 100Ω differential termination, each lane consumes ~6.4 mW. For 7,200 lanes, that's 46W of termination power dissipated across the backplane

• Copper thickness: Signal layers use 1 oz RTF copper — the Joule heating is distributed and manageable

• Airflow: Backplane area must be exposed to rack-level airflow; obstructions (cable management, etc.) must avoid the backplane zone

Manufacturing Challenges

Fabricating a 30+ layer backplane spanning 30×24 inches at 3.5+ mm thickness:

• Registration: ±1.5 mil across the full panel — any error at inner layers propagates to connector via capture pads

• Press-fit holes: 0.6 mm finished hole size with ±25 μm tolerance and 25 μm minimum copper plating

• Warpage: ≤0.5% after reflow — 30" panel must not bow more than 0.15" across the diagonal

• Backdrilling: All high-speed vias backdrilled to within 8 mil of target layer, with AOI verification