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Electrophysiology DAQ solution

512-Channel Neural Signal Acquisition | Intan RHD Chipset · FPGA Processing | USB 3.0 · 30 kHz/ch | Low-Noise Analog Front-End | Open Ephys Compatible The electrophysiology data acquisition (DAQ) board is a high-density mixed-signal PCB that digitizes microvolt-level neural signals from up to 512 channels simultaneously and streams them to a host computer over USB 3.0. Compatible with the Open Ephys open-source platform, this board integrates Intan RHD-series bioamplifier chips, an FPGA for data aggregation and protocol handling, USB 3.0 PHY, and DDR memory — all on a single high-layer-count PCB. Superb Automation provides turnkey PCBA for these neuroscience research instruments, with the precision analog handling and signal isolation that µV-level recording demands.
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Product Specifications

Electrophysiology DAQ PCBA

512-Channel Neural Signal Acquisition | Intan RHD Chipset · FPGA Processing | USB 3.0 · 30 kHz/ch | Low-Noise Analog Front-End | Open Ephys Compatible

Product Overview

The electrophysiology data acquisition (DAQ) board is a high-density mixed-signal PCB that digitizes microvolt-level neural signals from up to 512 channels simultaneously and streams them to a host computer over USB 3.0. Compatible with the Open Ephys open-source platform, this board integrates Intan RHD-series bioamplifier chips, an FPGA for data aggregation and protocol handling, USB 3.0 PHY, and DDR memory — all on a single high-layer-count PCB. Superb Automation provides turnkey PCBA for these neuroscience research instruments, with the precision analog handling and signal isolation that µV-level recording demands.

System Specifications

Channel CountUp to 512 channels — 8 × Intan RHD headstage ports, 64 channels per headstage
Sampling RateUp to 30 kHz per channel, simultaneous sampling across all channels
Signal Bandwidth0.1 Hz – 7.6 kHz (Intan RHD2164), configurable per application
Input-Referred Noise2.4 µV RMS typical (Intan RHD2164), critical for extracellular spikes
InterfaceUSB 3.0 to host computer — sustained streaming of all 512 channels
Core ChipsetIntan RHD2164 or RHD2132 × 8 + FPGA (Xilinx/Intel) + USB 3.0 PHY + DDR3/DDR4
Analog I/O8 bidirectional ADCs (±5V) via I/O expansion board
Digital I/O8 digital inputs for TTL trigger and synchronization
Headstage PowerRegulated 3.3V supply to each headstage port — low-noise LDO
SoftwareOpen Ephys GUI — open-source, plugin-based acquisition and analysis
Open-SourceFull hardware design files available at open-ephys.org

PCBA Manufacturing Challenges

1. Low-Noise Analog Front-End — µV-Level Signal Integrity

Neural action potentials (spikes) are typically 50–500 µV in amplitude. The PCB itself can introduce noise that obscures these signals if not designed and assembled with extreme care. Critical factors include: solder flux residue creating parasitic leakage paths between high-impedance nodes, PCB surface contamination trapping moisture and increasing dielectric loss, and ground plane discontinuities inducing common-mode noise. Superb Automation uses post-reflow aqueous cleaning to remove all flux residue from the analog front-end region, verified by ionic contamination testing (ROSE test) below 1.56 µg/cm² NaCl equivalent. The analog section uses dedicated ground planes split from the digital section, joined at a single star-ground point under the ADC.

2. High-Density FPGA BGA Assembly

The FPGA — typically a Xilinx Artix-7 or Kintex-7 in a 484–676 ball BGA package — acts as the central data aggregator, handling 8 parallel SPI streams from the Intan chips, DDR memory access, and USB 3.0 protocol offload. BGA assembly for such a dense package on a mixed-signal board requires precise reflow profiling to avoid warpage that could cause head-in-pillow defects on outer balls while the analog section nearby experiences excessive heat. We use vacuum-assisted nitrogen reflow with X-ray inspection on every BGA, verifying full ball collapse and void rate below 15%.

3. 8-Channel Parallel SPI — Length Matching & Impedance Control

Eight Intan RHD chips communicate with the FPGA over independent SPI buses running at up to 30 MHz. With 4 signals per bus (SCLK, MOSI, MISO, CS) across 8 buses = 32 high-speed traces that must be length-matched within each bus group to avoid clock-to-data skew. Additionally, USB 3.0 SuperSpeed differential pairs (5 Gbps) require tight 90Ω differential impedance control. Superb Automation performs TDR impedance verification on all controlled-impedance traces and length-matching verification on the SPI bus groups using flying probe test with time-domain analysis.

4. Power Delivery — Low-Noise Analog Rails

The Intan RHD chips require ultra-clean 3.3V analog supply rails — power supply ripple directly couples into the neural recording channel as noise. The board must deliver clean power to up to 8 headstages simultaneously. We use separate LDO regulation per headstage port, with generous decoupling capacitor arrays (10 µF tantalum + 0.1 µF + 0.01 µF MLCC per rail), and dedicated power plane segments to minimize IR drop to the outermost headstage connectors.

5. Headstage Connector Soldering — Mechanical & Electrical Integrity

Each of the 8 headstage ports uses a fine-pitch connector (typically SPI + power + ground, 12–16 positions). These connectors face repeated insertion/removal cycles during experiments. Cold solder joints or insufficient pad adhesion lead to intermittent channel dropout — a catastrophic failure during an in-vivo recording session. We use through-hole or SMT connectors with reinforced pad design and X-ray inspection of all connector solder joints. Pull-force testing verifies mechanical integrity beyond 500 insertion cycles.

Superb Automation Assembly Capabilities — Electrophysiology DAQ

PCB Layer Count12–16 layers — dedicated analog ground, digital ground, multiple power planes, high-speed routing layers
FPGA BGA Assembly484–676 ball BGA — vacuum nitrogen reflow, X-ray ball collapse + void inspection < 15%
Low-Noise AnalogPost-reflow aqueous cleaning, ROSE test < 1.56 µg/cm² NaCl, star-ground isolation between analog/digital domains
SPI Bus Matching8 × SPI buses length-matched within each group — flying probe TDR verification
USB 3.0 Differential Pairs90Ω ±5% controlled impedance — TDR coupon verification on every panel
Headstage ConnectorsFine-pitch SPI/power connectors — reinforced pad, X-ray joint inspection, >500-cycle pull-force test
Analog Power RailsPer-port LDO regulation — ripple < 1 mV RMS measured at headstage connector, decoupling verified
DDR MemoryDDR3/DDR4 SDRAM — BGA assembly, write/read pattern test, eye diagram margin verification
Functional TestFull-channel acquisition test: signal generator input → all 512 channels verified, USB 3.0 streaming test at full bandwidth

Ordering Options

ModeService
PCB Only12–16 layer mixed-signal PCB — ENIG finish, controlled impedance, IPC Class 3 inspection
PCBA TurnkeyFull turnkey — FPGA, Intan RHD, USB PHY, DDR, connectors, passives. Includes cleaning, X-ray, TDR, and functional test
Partial ConsignmentCustomer supplies FPGA / Intan chips (long-lead or allocated components); Superb assembles remaining BOM and tests
Custom DAQ PCBACustomer provides design — Superb handles fabrication and assembly for custom electrophysiology or biosignal acquisition boards under NDA

Applicable Research & Instrumentation Types

In-Vivo ElectrophysiologyExtracellular spike recording from implanted microelectrode arrays in awake, behaving animals
Ex-Vivo Slice RecordingAcute brain slice field potential and single-unit recording — low-noise essential for small signals
EEG / ECOG AcquisitionScalp or cortical surface potential recording — high channel count for source localization studies
Closed-Loop ExperimentsReal-time neural decoding with digital/analog output feedback — deterministic latency required
Neuroprosthetics R&DBrain-machine interface (BMI) prototyping — high channel count, low latency data pipeline

Send your electrophysiology DAQ Gerber and BOM to pcba@superb-tech.com for a free DFM review. NDA protection for custom neuroscience instrumentation designs.