HDI is worth the cost only when a design runs out of space. The usual trigger is a fine-pitch BGA: at 0.5 mm pitch a through-hole via cannot fit between pads, at 0.4 mm pitch even a dogbone escape fails, and a 0.1 mm laser micro-via with via-in-pad becomes the only route through. HDI buys density at the price of lamination cycles and tighter rules.
SUPERB supports HDI from 1-N-1 through any-layer, with minimum line width 0.0125 mm, up to 68 layers, and impedance within ±5%, or ±2% on critical nets. Via structures, dielectric thicknesses and BGA escapes are reviewed against the process before Gerber release, where most HDI cost and yield are decided.
What Is HDI Technology?
HDI is defined by IPC-2226 and comes in build-up levels. A 1-N-1 board has one micro-via layer on each side of a mechanically drilled core, and a 2-N-2 board adds a second layer on each side. Any-layer, also written ELIC or ALIC, lets any layer connect to any other through micro-vias, removing the through-hole bottleneck.
What separates HDI from conventional multilayer is the process. Build-up dielectric is laminated over a finished core, laser drilled, plated and planarized, then patterned with fine lines. Each micro-via layer adds a lamination cycle, so cost scales with build-up count, not total layer count.
Build-Up Levels and Where Each One Fits
1-N-1 covers most 0.5 mm pitch fanout on 4 to 8 layers. 2-N-2 is the workhorse for 0.4 mm pitch and multi-package boards on 6 to 12 layers. Any-layer is reserved for designs that need unrestricted connection between every layer, typically 8 to 16 layers and above.
HDI Structure Comparison: 1-N-1 to ELIC and ALIC
Relative cost is measured against 1-N-1, and layer counts are typical limits.
| Structure | Build-up per side | Typical layers | Via stacking | Relative cost | Best for |
|---|---|---|---|---|---|
| 1-N-1 | 1 | 4-8 | Single-level micro-via, through-vias in core | 1.0x | 0.5 mm pitch BGA, cost-sensitive |
| 2-N-2 | 2 | 6-12 | Micro-vias stacked in pairs, through-vias in core | 1.5x-2.0x | 0.4 mm pitch BGA, dense multi-package boards |
| ELIC or ALIC (any-layer) | Every layer pair | 8-16 and above | Any layer to any other, no mechanical through-via needed | 4x-6x | Maximum density, wearable and implant use |
Move up one level when the structure cannot escape the outer two rows of a BGA, or when the required layer count exceeds what the build-up supports. Staying a level lower than necessary overspends; reaching one level too low loses a schedule.
Micro-Via Types and Structures
Blind Micro-Via
- Connects the outer layer to an inner layer
- Does not pass through the entire board
- Laser drilled, typically 0.1-0.15 mm finished diameter
- A copper target pad on the layer below stops the laser at the correct depth
Buried Micro-Via
- Connects inner layers only, fully enclosed in the board
- Invisible from the surface, so it must be documented in the fabrication drawing
- Created during sequential lamination, before the outer layers are added
Stacked and Staggered Micro-Vias: Which to Choose
A stacked micro-via sits on top of the via below, so one column connects several layers. A staggered micro-via is offset, so the connection hops sideways between levels. Stacked saves area and shortens the vertical path but concentrates stress and demands tighter laser registration. Staggered spreads that stress, suiting automotive, medical and aerospace programs.
Use staggered vias up to three build-up levels unless the escape budget demands stacked, and specify plated copper fill rather than resin fill when a via is stacked. PCB capability pages list which constructions are supported.
Via-in-Pad and Copper Filled Plating
Placing a micro-via inside an SMT pad makes 0.4 mm and finer pitch fanout possible, because it frees the space a dogbone escape would occupy. It is also the feature most likely to cause assembly defects, since an unfilled via under a pad wicks solder into the barrel and leaves a void or an open joint.
Via-in-pad therefore needs a defined fill, planarization and plating sequence, with three items in the drawing:
- Fill type: conductive or non-conductive, and whether the via is capped and plated over, per the filled and capped categories of IPC-4761
- Dimple depth: commonly 25 µm or less from the pad surface, because a deeper dimple traps flux and voids the joint
- Voiding limit: a small percentage of the via cross-section, agreed before release so it can be measured
Specify plated copper fill when a micro-via must be stacked, because it carries the next level and survives another lamination cycle without opening voids. Resin fill suits a single-level via-in-pad but is a poor base for a stack. The target pad must also be large enough to catch the laser, typically the via diameter plus 0.15 to 0.2 mm.
Laser Via Diameter and Dielectric Thickness
Micro-via reliability is governed by aspect ratio, the dielectric thickness the via must penetrate divided by its finished diameter. A 0.1 mm via through 0.1 mm dielectric is 1:1, the accepted working limit, because beyond it plating thins at mid-depth where it cannot be inspected. Thin dielectric and small vias must therefore be specified together.
| Via diameter (finished) | Max dielectric thickness | Target pad | Typical use |
|---|---|---|---|
| 0.075 mm | 0.075 mm | 0.20-0.25 mm | 0.4 mm pitch BGA escape |
| 0.10 mm | 0.10 mm | 0.25-0.30 mm | Standard HDI, 0.5 mm pitch BGA |
| 0.15 mm | 0.15 mm | 0.30-0.35 mm | Lower-density build-up |
Registration is the other controlling number. Laser position and layer-to-layer registration typically sit in the ±25 µm range, with advanced lines at ±15 µm, so target pads and copper clearances are dimensioned around that tolerance. The dielectric thickness after lamination belongs in the drawing too, since prepreg flow reduces it, as does the barrel plating thickness.
Design Rules for HDI
Micro-via aspect ratio should not exceed 1:1 for best reliability, so a 0.1 mm diameter via should connect layers no more than 0.1 mm apart. Laser-drilled vias require a copper target pad on the layer below to stop the laser at the correct depth and prevent damage to underlying layers.
- Aspect ratio at or below 1:1 for reliable plating
- Copper target pad on the layer below each laser via, sized to drill tolerance
- Via-in-pad requires filling and planarization, with dimple and voiding limits in the drawing
- Reliability decreases with each stacked level, so keep stacks to three levels or fewer without a review
- Laminate must be laser-drill compatible, meaning a resin system suited to laser energy rather than standard high-glass-fill construction
BGA Fanout: Minimum Pad and Spacing Rules
Escape routing is where an HDI stack-up is proved. The values below are typical working rules for the outer rows inward, assuming a 0.1 mm laser via with via-in-pad where pitch demands it.
| BGA pitch | Pad diameter | Trace and spacing | Escape method |
|---|---|---|---|
| 0.80 mm | 0.40-0.50 mm | 0.10 mm / 0.10 mm | Dogbone via between pads, no HDI required |
| 0.50 mm | 0.25-0.30 mm | 0.075-0.10 mm / 0.075-0.10 mm | 1-N-1 with via-in-pad for inner rows |
| 0.40 mm and below | 0.20-0.25 mm | 0.06 mm and below | 2-N-2 with via-in-pad, stacked for innermost rows |
Three escape rules keep fanout out of trouble. Escape the outer two rows on the top layer before dropping to a micro-via. Keep a ground plane adjacent to the fastest escape layers, because a via crossing several layers creates return path discontinuities. Keep signal vias out of the thermal pad area of power devices.
Frequently Asked Questions
When should a design move from through-hole vias to HDI?
The triggers are a BGA at 0.5 mm pitch or finer, an escape dogbone vias cannot meet, or a very high ball count in a small outline. Below 0.4 mm pitch, HDI is effectively mandatory.
Which is better, stacked or staggered micro-vias?
Stacked wins on density and vertical path length, staggered wins on reliability. For automotive, medical and aerospace programs choose staggered, with plated copper fill when a via must be stacked.
Why does via-in-pad need filling and planarization?
An unfilled via under a pad acts as a capillary, so solder wicks into the barrel and leaves a void or an open joint. Filling and planarizing produces a surface that behaves like a solid pad.
What limits how small a laser micro-via can be?
Plating uniformity inside the barrel, not the laser. Aspect ratio at or below 1:1 keeps the barrel evenly plated, so a 0.075 mm via needs dielectric near 0.075 mm and a target pad near 0.2 mm.
How many build-up layers should a design use?
Start at 1-N-1 and step up only when escape density or layer count demands it. 1-N-1 covers most 0.5 mm pitch work, and 2-N-2 covers 0.4 mm pitch and dense multi-package boards.
HDI pays back on designs genuinely out of escape space and costs on designs that only look crowded. Send us your BGA pitch, ball count, layer plan and impedance targets, and we will return a build-up proposal with via structure, dielectric thickness and target pad sizes per layer.
