When Does a PCB Become "High-Speed"?
A board becomes high-speed the moment its interconnects behave like transmission lines rather than ideal wires, and the trigger is the edge, not the clock. Apply the electrical-length rule: treat a trace as a controlled-impedance line when twice its one-way propagation delay exceeds the signal rise time. On FR-4 microstrip the delay is about 150 ps per inch (6 ps per mm).
Modern edges make even short routing electrically long. A 50 ps DDR5 edge turns any trace longer than about 0.17 inch (4 mm) into a transmission line, and a 16 ps PCIe Gen5 edge lowers that threshold to about 0.05 inch (1.3 mm).
Why the Edge, Not the Clock, Sets the Limit
The clock says how often a line switches; the rise time says how much spectrum it contains. The knee frequency, about 0.5 divided by the rise time, is the highest harmonic with meaningful energy. A 1 MHz clock with a 20 ps edge has a knee near 25 GHz, while a 100 MHz clock with a 5 ns edge tolerates loose routing.
Executable Thresholds by Interface
The table shows when each interface must be routed as a controlled-impedance line, assuming 150 ps per inch.
| Interface | Typical edge or rate | Controlled impedance above | Target |
|---|---|---|---|
| DDR5 / DDR4 | ~50 ps edge | ~0.17 in (4 mm) | 40 Ω single-ended / 80 Ω differential |
| PCIe Gen5 | 32 GT/s, ~16 ps edge | ~0.05 in (1.3 mm) | 85 Ω differential |
| USB 3.2 Gen 2 | 10 Gbps, ~40 ps edge | ~0.13 in (3.3 mm) | 90 Ω differential |
| 100G Ethernet | 4 x 25G NRZ, ~25 ps edge | ~0.08 in (2 mm) | 100 Ω differential |
Impedance Control: The Foundation of Signal Integrity
Controlled impedance means designing each trace so its characteristic impedance matches what the driver and receiver expect, typically 50 Ω single-ended and 85 to 100 Ω differential. Four factors set it: trace width, copper thickness, dielectric thickness to the nearest reference plane, and the laminate's dielectric constant (Dk).
How to Set Single-Ended Versus Differential Targets
Take the target from the silicon, not from habit. The interface standard or the chip vendor's layout guide names the value: 50 Ω is the general-purpose single-ended default, DDR memory usually specifies 40 Ω single-ended, and high-speed serial links specify 85 to 100 Ω differential. Design to the center of the vendor's range and hold tolerance across the whole trace. Differential impedance is not twice the single-ended value, because coupling lowers it.
Tolerance, Materials, and Copper Weight
SUPERB verifies controlled-impedance boards to ±5%, holding ±2% on critical signals. Standard FR-4 is adequate to about 10 Gbps, while lower-loss materials such as Megtron, Rogers, and PTFE are available through our supply chain for 25G and above. Heavier copper, stated as Max Copper Thickness in OZ, narrows the trace for a given impedance. SUPERB supports line widths to 0.0125 mm and stackups to 68 layers.
Differential Pair Routing
Differential signaling carries information as the difference between two complementary traces, so the receiver rejects whatever is common to both. That only works if the two traces stay electrically identical from driver to receiver, which makes skew the governing budget: within the pair, and between pairs.
Intra-Pair (Within-Pair) Skew
Within a pair, length mismatch turns differential signal into common-mode signal, which radiates and eats timing margin. Keep intra-pair skew under 5 mils (0.127 mm) at 10 Gbps, 2 mils at 25 Gbps, and 1 mil at 56 Gbps and above. Count bends, vias, layer transitions, and package pin escapes, not just straight-line length, and compensate on the shorter trace with a serpentine placed close to the mismatch.
| Data rate | Max intra-pair skew | Max inter-pair skew |
|---|---|---|
| Up to 5 Gbps | 10 mils (0.25 mm) | 50 mils (1.27 mm) |
| 10 Gbps | 5 mils (0.13 mm) | 25 mils (0.64 mm) |
| 25 Gbps | 2 mils (0.05 mm) | 10 mils (0.25 mm) |
| 56 Gbps and above | 1 mil (0.025 mm) | 5 mils (0.13 mm) |
Inter-Pair (Pair-to-Pair) Skew
Between pairs in the same group, such as a PCIe lane set, a DDR byte lane, or a multi-lane Ethernet port, length mismatch consumes setup and hold margin. Match each lane or byte group to the skew budget above.
Spacing, Symmetry, and Layer Transitions
Keep the gap constant along a pair, because spacing sets the coupling that sets the differential impedance; a pair that pinches to escape a dense BGA shows a local impedance drop and a reflection. Hold the pair symmetric, on one layer over a continuous reference plane, and at a layer change transition both traces through matched vias with a ground via beside each signal via.
Return Path & Reference Planes
Every signal current has a return current, and the return takes the path of least impedance, not the shortest path by length. At DC that means least resistance; at high frequency the return current concentrates directly beneath the signal trace, in the nearest reference plane.
What Happens at a Reference Plane Discontinuity
Any break in the reference plane beneath a high-speed trace forces the return current to detour, adding inductance, creating an impedance discontinuity, and radiating. The offenders are a slot in the ground plane, a plane cutout around a connector, and a change of reference plane. The rule: never route a high-speed net over a plane split, and if a reference cannot be continuous, add a stitching capacitor or a nearby ground via path across the break.
Layer Transitions and Stitching Vias
When a trace changes layers, its reference plane may change. If both planes are ground, a ground via within about 50 mils (1.27 mm) of the signal via gives the return current a low-inductance path. If the planes are ground and power, the return current needs a decoupling capacitor between them, within roughly 100 mils (2.54 mm) of the via. Keep the ground plane solid under high-speed signals and route the fastest nets as stripline.
TDR Verification: Proving Impedance After Fabrication
Impedance control is only real if it is measured. Time-domain reflectometry (TDR) launches a fast voltage step into a coupon or trace and converts the reflected voltage into an impedance profile along the length. A flat trace at the target means a uniform line; a bump or dip means a local change in width, dielectric, or reference plane.
How a TDR Acceptance Test Is Run
- Build coupons on the same panel and stackup as the production boards, so they reflect the actual dielectric and copper.
- Step each coupon with a TDR whose rise time is at least as fast as the tightest trace, recording single-ended and differential structures separately.
- Measure at the finished width after plating and etch, since as-designed and as-built widths differ.
- Compare each reading against the target and tolerance window, and report results per panel.
SUPERB verifies impedance to ±5% on standard controlled-impedance boards and to ±2% on critical signals, with TDR results reported per panel. Where a reading falls outside the window, the geometry is corrected at fabrication.
Frequently Asked Questions
At what rise time must I do impedance control?
Use the electrical-length rule: if twice the one-way trace delay exceeds the rise time, the trace is a transmission line and needs controlled impedance. Any edge faster than about 1 ns should be checked, and below 50 ps assume every net is high-speed.
What is the difference between 50 Ω single-ended and 100 Ω differential?
They measure different structures. A single-ended trace referenced to a plane is designed to 50 Ω, while a differential pair measures impedance between its two traces and is not twice the single-ended value because they couple. Design the pair to its required target, usually 85 to 100 Ω.
How tight should differential pair length matching be?
Within a pair, keep skew under 5 mils at 10 Gbps, 2 mils at 25 Gbps, and 1 mil at 56 Gbps and above. Between pairs in a bus, allow roughly five to ten times more, counting vias and layer transitions.
Can I route a high-speed trace over a split in the ground plane?
No. A split forces the return current to detour, creating an impedance discontinuity and radiating common-mode noise. If the reference cannot be continuous, provide a stitching capacitor or an adjacent ground via path.
How is controlled impedance verified?
By TDR on coupons built on the same panel and stackup as the production boards. The measured impedance is compared against the target and tolerance window, and a per-panel report documents pass or fail.
What materials are available for high-speed and RF stackups?
FR-4 covers most designs to about 10 Gbps. For higher speeds and RF, lower-loss laminates such as Megtron, Rogers, and PTFE are available through our supply chain.
Controlled impedance, matched pairs, and continuous return paths are the three levers that decide whether a high-speed board works on the first spin. Send us your Gerbers or stackup drawing and we will review the impedance targets and tolerance window before fabrication. See our guide to HDI PCB manufacturing.
