Three constraints decide a stack-up before any preference does. Every signal layer needs a reference plane within 0.2 mm for a controlled return path. Copper and dielectric distribution must mirror about the board center. And the laminate sets Dk and Df, which set the insertion loss your link budget can survive.
SUPERB coordinates layer plan, laminate grade, copper weight and impedance targets as one package: 4 to 68 layers, minimum line width 0.0125 mm, copper from 0.5 OZ to 6 OZ, impedance within ±5%, and ±2% on critical nets.
Why Stack-Up Design Is the Foundation of PCB Performance
The stack-up should be one of the first decisions in your design process, before you place a component. It fixes trace impedance, from conductor width and dielectric height to the adjacent plane; crosstalk, from spacing and from how much field the plane captures; and board flatness.
Two rules govern every stack-up. Every signal layer must have an adjacent reference plane for a clean return path, and the stack-up must be symmetric about the board center so the board does not bow during reflow.
What a Late Stack-Up Change Costs
Moving one signal layer changes the dielectric height under every trace on it, so every controlled impedance trace there must be re-tuned. Turning a plane into a signal layer breaks the return path of every layer that referenced it. A change after layout means re-routing 30 to 60 percent of the board and weeks of delay. Mixed RF, high-speed and low-speed designs should be split into signal domains first, as covered under PCB design engineering.
PCB Materials: Beyond Standard FR-4
Standard FR-4 (Tg 130-140 °C, Dk 4.2 to 4.5) works well below 1 GHz. As frequencies climb, Dk sets the geometry needed for a target impedance and Df sets how much signal energy becomes heat inside the dielectric.
| Material | Dk @ 10 GHz | Df @ 10 GHz | Tg (°C) | Best For |
|---|---|---|---|---|
| Standard FR-4 | 4.2-4.5 | 0.020 | 130-140 | General digital |
| Isola 370HR | ~3.9 | ~0.015 | 180 | Industrial, lead-free reflow |
| Megtron 6 | ~3.7 | ~0.004 | 185 | 25G-56G high-speed digital |
| Rogers RO4350B | 3.48 | 0.0037 | >280 | RF and microwave, mmWave |
| Megtron 7 | ~3.4 | ~0.002 | 200 | 56G-112G PAM4 |
| Tachyon 100G | ~3.0 | ~0.0014 | 200 | 112G and above |
Reading Dk and Df, and Matching Laminate to Data Rate
Dk is frequency dependent, so a value quoted at 1 MHz is not the number to design with at 10 GHz, and the gap is commonly 5 to 10 percent. Df limits reach, because dielectric loss rises with frequency while conductor loss grows with its square root.
| Interface class | Nyquist | Laminate to specify | Target Df at 10 GHz |
|---|---|---|---|
| 10G Ethernet, USB 3.2, PCIe Gen 3-4 | 5 GHz | Mid-loss FR-4, Tg 170 °C and above | 0.010-0.015 |
| 25G and 100G NRZ, PCIe Gen 5 | 12.5 GHz | Low-loss, Dk 3.6-3.8 | 0.004-0.008 |
| 56G PAM4 and above, 400G-800G | 14 GHz and above | Ultra-low-loss, Dk 3.0-3.6 | 0.002 or lower |
In practice, 10G tolerates improved FR-4 on short traces, 25G calls for low-loss laminate with a loss budget, and 56G and above needs ultra-low-loss with spread-glass construction for skew control. Isola, Panasonic, Rogers and Taconic laminates are available through our supply chain.
Layer Count and Signal Layer Planning
Layer count follows from three numbers: how many nets must cross, how many rails need low-impedance distribution, and how many controlled impedance interfaces the board carries. A plane is not a routing layer, so an 8-layer board with three planes gives about 4 to 5 signal layers.
Which Signals Belong on Which Layer
- Highest-speed serial lanes and clocks: inner layer next to solid ground, for an uninterrupted return path and shielding on one side.
- RF and microwave nets: outer layer over ground with coplanar pour and stitching, so impedance can be trimmed after the first prototype.
- Analog and low-level nets: a dedicated area, never parallel to a clock or switching node.
- Power and ground: full planes for the main rails, near the board center so copper balance stays mirrored.
Two prohibitions are absolute. Never route a high-speed trace across a split in its reference plane, because the return current detours around the gap. Never route single-ended high-speed nets on a layer whose only adjacent plane is fragmented.
Pairing Every Signal Layer With a Reference Plane
A typical 6-layer high-speed stack-up is L1 signal, L2 ground, L3 inner signal, L4 inner signal, L5 power, L6 signal. L1 references L2, L3 references L2 and L4, L4 references L3 and L5, L6 references L5. Thin dielectric keeps traces narrow for a 50 ohm target while cutting crosstalk.
| Layers | Typical arrangement | Best for |
|---|---|---|
| 4 | Signal, ground, power, signal | General digital below 1 GHz |
| 6 | Signal, ground, signal, signal, power, signal | Mid-range high-speed, DDR, several rails |
| 8 | Signal, ground, signal, power, ground, signal, ground, signal | 25G interfaces, multiple power domains |
| 10 | Signal, ground, signal, ground, power, power, ground, signal, ground, signal | 56G and above, large BGAs, mixed RF and digital |
Copper Weight, Current Capacity and Max Copper Thickness
Copper weight is quoted in OZ, where 1 OZ is about 35 µm. Outer layers finish thicker than the base foil because plating adds copper during via formation, so 1 OZ foil ends near 40 µm on the surface. Our capability pages list the limit as Max Copper Thickness in OZ.
Current capacity depends on cross-section, permitted temperature rise and position. Internal traces are insulated by dielectric and carry roughly 55 to 60 percent of the external current for the same 10 °C rise. Values below are typical at 10 °C rise for a 1 mm wide trace.
| Max Copper Thickness (OZ) | External, 1 mm, 10 °C rise | Internal, 1 mm, 10 °C rise | Typical use |
|---|---|---|---|
| 0.5 | 1.2 A | 0.7 A | Fine-line signal |
| 1 | 2.3 A | 1.3 A | Signal and light power |
| 2 | 3.6 A | 2.1 A | Power distribution, motor drive |
| 3 | 4.6 A | 2.7 A | High-current rails |
| 6 | 7.0 A | 4.0 A | Heavy copper bus, IGBT drive |
Above about 3 A, split the net into parallel traces or a pour. Above about 10 A, use a plane or 2 OZ and heavier copper and check vias, since a 0.3 mm via barrel carries far less current than the trace feeding it. Heavy copper also etches with a trapezoidal profile, so 3 OZ and above needs wider spacing than the 0.0125 mm fine-line rules elsewhere.
When a Symmetric Stack-Up Is Mandatory
Copper distribution and dielectric thicknesses must mirror about the board center. Unequal copper weights or prepreg thicknesses top versus bottom are the leading cause of warpage during reflow. On these designs symmetry is mandatory, not optional:
- Finished thickness above 1.6 mm with 8 or more layers: keep both halves within about 10 percent in dielectric thickness and copper coverage.
- Heavy copper of 2 OZ and above: etch asymmetry amplifies any copper imbalance.
- Panels above roughly 200 mm: a long thin board warps even when the stack is nearly symmetric.
- Sequential lamination or HDI build-up: every cycle adds material to one side, so mirror the build-up, 2-N-2 rather than 2-N-1.
- Low-Dk and high-Tg laminates: higher CTE reveals asymmetry earlier than FR-4.
Asymmetry also breaks impedance, since a thinner dielectric on one side narrows traces for the same 50 ohm target. Where asymmetry is unavoidable, tune each half separately, keep the copper balance mirrored even where the dielectric is not, and state it in the fabrication notes.
Frequently Asked Questions
How many layers do I need?
Count the nets that must cross, add one plane pair per noisy or high-current rail, and remember that planes are not routing layers. A DDR board with a 25G interface lands at 8 layers.
Can a stack-up be asymmetric if copper stays balanced?
Partly. Balanced copper removes the largest warpage driver, but on thick or large boards thickness and dielectric distribution should still mirror within about 10 percent.
What is the difference between Dk and Df?
Dk sets geometry, Df sets loss. Higher Dk narrows traces for a given impedance, while Df predicts whether a channel closes, and above 25G it dominates the budget.
How much current can 2 OZ copper carry?
About 3.6 A external and 2.1 A internal for a 1 mm wide trace at a 10 °C rise. Beyond that use a plane or parallel traces, and check vias, which often limit a power net first.
Do you support controlled impedance on every layer?
Yes, within ±5% as standard and ±2% where critical nets require it. Provide target impedances and reference planes per net class and the geometry is calculated to meet them before release.
A stack-up is the cheapest place to solve impedance, return path and warpage problems, and the most expensive place to solve them later. Send us your layer requirements, net classes and target impedances for a reviewed stack-up with laminate grade, copper weight and dielectric heights listed per layer.
