Modular robot compute architectures split processing across multiple cards — a vision card (GPU/NPU), a motion-planning card (CPU), a real-time control card (MCU/FPGA), and safety/IO cards — all interconnected through a high-speed backplane PCB. The backplane carries PCIe Gen4/5 at 16–32 GT/s and multi-gigabit Ethernet, demanding rigorous signal integrity engineering. This article covers backplane design and manufacturing for robot systems.

Robot Backplane Architecture

• Topology: Passive backplane with 4–8 card slots in a star or dual-star configuration. Cards plug in via high-density edge connectors (PCIe x4/x8 card-edge or Samtec SEARAY open-pin-field arrays). The backplane itself contains no active components — all intelligence is on the plug-in cards

• Form factor: Custom 120 mm × 200 mm to 200 mm × 300 mm, fitting inside the robot's torso cavity. OpenVPX or custom mechanical format. Thickness: 2.4–3.2 mm for structural rigidity without a separate stiffener plate

• Interconnect bandwidth: Vision card → motion card: PCIe Gen4 x8 (16 GB/s each direction) for streaming processed point clouds and pose estimates. Motion card → control card: PCIe Gen3 x4 (4 GB/s) for trajectory commands. Control card → IO cards: Gigabit Ethernet or CAN FD for joint-level commands

PCIe Backplane Signal Integrity

• Data rate: PCIe Gen4 = 16 GT/s (Nyquist frequency 8 GHz). PCIe Gen5 = 32 GT/s (Nyquist 16 GHz). At these frequencies, every via stub, connector pin, and impedance discontinuity matters

• Channel budget: PCIe Gen4 end-to-end loss budget: -28 dB at 8 GHz. Allocation: -6 dB for the card trace, -2 dB for the edge connector, -12 dB for the backplane trace, -8 dB margin. Total backplane trace length typically limited to 250–350 mm on standard FR-4

• Material selection: Megtron 6 (Dk = 3.57, Df = 0.002 at 10 GHz) or IT-968G for Gen4 backplanes. Megtron 7 (Df = 0.001) for Gen5. The lower Df reduces dielectric loss — at 16 GHz, Megtron 6 loses ~1.2 dB/inch vs. ~0.8 dB/inch for Megtron 7

• Via design: Back-drilled vias to remove stubs. For a 3.2 mm thick backplane, an un-backdrilled via creates a λ/4 stub resonance at ~12 GHz — right in the Gen4 Nyquist band. Back-drill to within 150 μm of the signal layer

Ethernet Bus Design

• 10GbE (10GBASE-KR): Single-lane 10.3125 Gbps over a single differential pair on the backplane. KX/KR auto-negotiation and link training. Used for inter-card data sharing (diagnostic logging, firmware updates, sensor data replay)

• 25GbE (25GBASE-KR): Single-lane 25.78125 Gbps. Nyquist at 12.89 GHz — requires Megtron 6 minimum. Used for high-bandwidth sensor streaming (8K camera raw, 128-line lidar point cloud)

• Signal conditioning: PCIe and 10GbE/25GbE signals typically use retimers or redrivers on each plug-in card, not on the backplane. The backplane remains passive. Card-side equalization (CTLE + DFE in the SERDES) compensates for backplane loss

Backplane PCB Manufacturing

• Layer count: 16–24 layers. Thick core (0.8–1.2 mm) for mechanical rigidity. High layer count needed for signal routing: 2–4 signal layers per card slot × 4–8 slots = 8–16 signal layers plus ground/power planes

• Aspect ratio: 3.2 mm board thickness with 0.2 mm drilled vias → 16:1 aspect ratio. Requires high-quality plating to avoid barrel cracks. Laser microvias not practical at this thickness — mechanical drilling only

• Press-fit connectors: Card-edge or compliant-pin connectors are press-fit, not soldered. Press-fit eliminates thermal stress on the thick backplane during assembly. Requires ±0.05 mm finished hole tolerance — tight but achievable on modern drilling equipment

• Impedance tolerance: 100Ω differential ±8% on backplane traces. Coupon-based TDR verification on every panel. Tight trace width control: ±10 μm for high-speed layers