The era of monolithic SoCs is giving way to chiplet-based architectures — disaggregating compute, memory, I/O, and accelerators into separate dies connected through a high-density substrate. Substrate-Like PCB (SLP) technology bridges the gap between traditional PCB manufacturing and semiconductor packaging, enabling chiplet integration at a dramatically lower cost than silicon interposers. This article explores the SLP chiplet substrate roadmap.

Why Chiplets Need New Substrate Technology

Monolithic GPU/CPU dies are hitting the reticle limit (~26 mm × 33 mm = 858 mm²). Going larger requires stitching multiple reticle exposures, reducing yield exponentially. Chiplets solve this by using multiple smaller dies:

• Yield advantage: A 900 mm² monolithic die at 5nm with defect density 0.1/cm² yields ~41%. Six 150 mm² chiplets yield ~86% each — dramatically better economics

• Mix-and-match: Different chiplets can use different process nodes. Compute dies at 3nm, I/O dies at 7nm, analog at 28nm — optimizing cost and performance per function

• Interconnect challenge: Chiplet-to-chiplet bandwidth must approach on-die bandwidth. UCIe (Universal Chiplet Interconnect Express) targets 1.3–5.2 TB/s/mm of die edge with <2 ns latency — requiring 2–5 μm line/space substrate routing

SLP Technology: PCB Manufacturing Meets Semiconductor Precision

SLP (Substrate-Like PCB) uses modified PCB manufacturing processes to achieve finer features than conventional PCBs but at lower cost than semiconductor interposers:

SLP occupies the critical middle ground — fine enough for chiplet interconnect, cheap enough for commercial deployment. It uses mSAP (modified Semi-Additive Process) to achieve 15/15 μm L/S on standard PCB panel sizes.

mSAP Process Flow

The mSAP process enabling SLP technology:

1. Electroless Cu seed: 0.2–0.5 μm deposited on ABF dielectric

2. Dry film photoresist: 15–25 μm thick, patterned with LDI (Laser Direct Imaging) at 2–5 μm resolution

3. Electrolytic Cu plating: Pattern-plate traces to 15–20 μm thickness

4. Resist strip: Remove dry film

5. Seed etch: Flash etch to remove seed layer (<0.5 μm) without significantly undercutting plated traces — the critical step that limits L/S capability

UCIe: The Standard for Chiplet Interconnect

UCIe 1.1 defines the physical layer for die-to-die communication:

• Standard package: 16–25 μm bump pitch, targeting organic substrates and PCB-based interposers. Up to 32 GT/s per lane (PCIe 5.0 speed), 16–64 lanes, ~1.3 TB/s/mm beachfront density.

• Advanced package: 4–9 μm bump pitch, targeting silicon interposer and fan-out packaging. Up to 32 GT/s per lane, 64–256 lanes, ~5.2 TB/s/mm.

• SLP alignment: SLP's 15/15 μm capability naturally targets the "Standard Package" UCIe tier — enabling chiplet integration without silicon interposers.

• BER: UCIe targets BER <10⁻²⁷ (effectively error-free with FEC) — 15 orders of magnitude better than PCIe. This requires pristine signal integrity in the substrate.

Fan-Out Panel-Level Packaging (FOPLP)

FOPLP extends SLP concepts to full panel-level chip packaging:

• Process: Chiplets are placed face-down on a temporary carrier. Epoxy mold compound encapsulates them. RDL layers are built up using mSAP on the reconstituted panel (510 × 610 mm).

• Density: 10/10 μm to 5/5 μm L/S achievable with FOPLP RDL — approaching FCBGA substrate density at a fraction of the cost

• Thermal: The mold compound has higher thermal resistance than silicon — careful thermal via design (copper pillars through mold compound) is required

• Warpage: Multi-material stack (silicon chips in epoxy mold + RDL layers) creates severe CTE mismatch. Panel warpage during processing must be below 2 mm across 510 mm — requiring active compensation in the design

The PCB-to-Semiconductor Convergence

SLP and chiplet technologies are blurring the line between PCB and semiconductor manufacturing:

• Feature convergence: PCB fabs are adopting mSAP to achieve 15/15 μm L/S. OSATs (outsourced semiconductor assembly and test) are moving to panel-level processing (510 × 610 mm), adopting PCB-scale equipment. The two industries are converging from opposite directions.

• Design flow: Chiplet-based designs require co-design across chip, package, and board. Traditional sequential design flows (chip → package → board) are being replaced by concurrent co-design with unified simulation environments.

• Supply chain: PCB manufacturers are investing in cleanroom capabilities (Class 1000–10000), laser direct imaging, and automated optical inspection matching semiconductor standards — a significant CapEx transition.