High Bandwidth Memory (HBM) is the enabling technology behind modern GPU memory systems — stacking DRAM dies vertically and connecting them through a silicon interposer with a 1,024-bit wide bus. HBM3E achieves 2 TB/s bandwidth in a package footprint smaller than a postage stamp. The PCB-level interconnect that supports this requires fundamentally different engineering than traditional DDR memory. This article dissects the HBM substrate and PCB interface.

HBM Generations and Bandwidth Scaling

An H100 GPU uses 6 HBM3 stacks for 3.35 TB/s aggregate bandwidth. The H200 bumps this to 6 HBM3E stacks at 4.8 TB/s — achieved through the silicon interposer, not the system PCB.

Why HBM Doesn't Route on the PCB

The key insight: the 1,024-bit HBM bus does not route on the system PCB at all. It's entirely contained within the silicon interposer. This is the fundamental value proposition of 2.5D packaging:

• PCB routing impossibility: A 1,024-bit bus at 9.6 Gbps consumes ~8,200 signals (including strobes, masks, ECC). At standard PCB trace density (~5 mil trace/space), this is physically impossible to route between CPU and memory within any reasonable board area.

• Power: PCB trace resistance (50–100 mΩ per trace × 8,200 signals) would consume hundreds of watts in I²R losses. On the silicon interposer, total path resistance is <5 mΩ.

• Skew: Matching 8,200 traces to within 10 ps across a 10-inch PCB is practically impossible. On a 25 mm silicon interposer, within-die matching is inherent.

Silicon Interposer: The "PCB" Inside the Package

The silicon interposer is a passive silicon die with multiple metal redistribution layers (RDL):

• Size: ~26 mm × 32 mm for H100 (GPU + 6 HBM sites). Thickness: 100 μm after backside grinding.

• Metal layers: 3–5 Cu RDL layers at 0.4–2 μm line/space. Fabricated using BEOL-style damascene processing on 300 mm wafers.

• TSV density: ~10,000 TSVs connecting top-side RDL to bottom-side C4 bumps. TSV pitch: ~50 μm.

• Microbump pitch: 45–55 μm between interposer and HBM/GPU dies. ~4,000 microbumps per HBM stack, ~20,000 per GPU die.

• Signal integrity: At 9.6 Gbps over ~5 mm traces on silicon, insertion loss is near-zero (<0.1 dB) and crosstalk is negligible due to the fine-pitch ground shielding possible in silicon processing.

FCBGA Substrate: The Bridge to the PCB

The silicon interposer sits on the FCBGA organic substrate, which fans out the connections:

• Interposer C4 bumps: ~180 μm pitch on the interposer bottom side → connects to substrate top pads

• Substrate fanout: The substrate redistributes the fine-pitch interposer connections to 1.0 mm BGA pitch on the bottom side. This is a 5.5:1 pitch expansion — requiring 6–10 substrate build-up layers

• HBM signals on the substrate: The substrate carries only the HBM PHY interface signals (management, temperature sensing, power delivery) — not the 1,024-bit data bus. The data bus never leaves the interposer.

Power Delivery for HBM

Each HBM3E stack draws 5–8W at 1.1V core (VDD) and 1.8V I/O (VDDQ). For 6 stacks, that's 30–48W through the interposer and substrate:

• Power path: System PCB → FCBGA substrate (BGA pins → substrate planes → substrate top pads) → interposer (TSVs → interposer RDL planes → microbumps) → HBM stack

• IR drop budget: ~50 mV total from VRM to HBM die. The interposer segment consumes ~5 mV; the substrate segment ~15 mV; the PCB segment ~30 mV.

• Decoupling: Deep trench capacitors embedded in the interposer silicon provide ~100 nF of on-interposer decoupling per HBM site. Additional MLCCs on the FCBGA substrate bottom side.

• Thermal: HBM stacks sit adjacent to the GPU die on the interposer. The GPU's thermal output (500–700W) heats the HBM through lateral conduction in the interposer and TIM. HBM junction temperature must stay below 95°C for reliable operation — a challenging constraint when the GPU die is at 85–90°C.

PCB-Level Signal Routing

While the HBM data bus stays on the interposer, the system PCB routes the HBM memory controller's PHY interface:

• PHY signals: Memory controller → GPU die → interposer → substrate → PCB → CPU/other agents. These are PCIe/CXL speed signals, not HBM-speed signals.

• Test access: JTAG/boundary scan for HBM stack testing — PCB routes these from the system BMC to the GPU package.

• Thermal monitoring: I2C/SMBus from each HBM stack's temperature sensor to the system BMC — routed through the substrate and system PCB.