While 5G radio access network (RAN) infrastructure garners most of the public and industry attention, the 5G core network (5GC) and transport network that interconnect base stations, route user traffic, and deliver services represent equally critical — and equally demanding — PCB design domains. The 5G core's shift to a Service-Based Architecture (SBA) running on virtualized, cloud-native infrastructure means that core network PCBs are essentially high-performance data center server platforms with specialized acceleration for packet processing, encryption, and traffic management. The transport network, meanwhile, must scale from 25 Gbps access links to 400 Gbps and 800 Gbps aggregate links, demanding PCB designs that push the limits of high-speed signal integrity. This article examines PCB solutions for 5G core and transport network equipment.

1. The 5G Service-Based Architecture and Its PCB Implications

The 3GPP 5G core architecture decomposes traditional monolithic network functions into a set of microservices communicating over HTTP/2-based Service-Based Interfaces (SBI). Network functions like the Access and Mobility Management Function (AMF), Session Management Function (SMF), and Policy Control Function (PCF) are primarily software entities running on commercial off-the-shelf (COTS) server hardware. The User Plane Function (UPF), however, handles the actual packet forwarding — routing user data between the RAN and data networks — and imposes the most stringent PCB requirements within the 5GC.

1.1 UPF User Plane PCB Design

The UPF is the workhorse of the 5G core user plane, performing packet inspection, classification, forwarding, QoS enforcement, and usage reporting at multi-terabit-per-second aggregate throughputs. A high-end UPF server blade must process packets at line rate across multiple 100 Gbps Ethernet interfaces with deterministic latency — typically sub-50 microseconds per packet through the UPF.

This performance is achieved through SmartNIC (Smart Network Interface Card) PCBs that combine high-speed Ethernet MAC/PHY interfaces, a programmable packet processing pipeline (implemented in FPGA or custom ASIC), and high-bandwidth memory for flow state tables and buffering. The SmartNIC PCB faces several design challenges:

• High-speed SERDES routing: 100G Ethernet using 4× 25G NRZ lanes (100GBASE-KR4/CR4) or 2× 50G PAM4 lanes (100GBASE-KR2/CR2). At 53.125 Gbps PAM4 (for 100G per lane in 400G implementations), the Nyquist frequency is 13.28 GHz, requiring ultra-low-loss materials with Df < 0.003 and insertion loss below 0.5 dB/inch at 14 GHz.

• Memory bandwidth: Flow state tables can require gigabytes of storage accessed at hundreds of millions of lookups per second. The external memory interfaces (DDR4/DDR5 for DRAM, RLDRAM or HBM for low-latency SRAM replacement) demand meticulous signal integrity design to maintain timing margins at multi-Gbps data rates.

• Packet buffer management: Deep packet buffers (tens of megabytes) for traffic shaping and congestion management require high-density, high-bandwidth memory interfaces that consume significant PCB routing resources.

1.2 Control Plane Server PCBs

The control plane network functions (AMF, SMF, PCF, NRF, NSSF, etc.) run on standard x86 or ARM-based server platforms, often virtualized as containers or virtual machines. The PCBs for these servers follow standard data center server design practices but with enhanced requirements for:

• Reliability: Carrier-grade availability (99.999% uptime) demands redundant power supplies, hot-swappable components, and comprehensive hardware health monitoring — all adding PCB complexity for power distribution, management buses, and FRU ID EEPROMs.

• Security: Hardware Root of Trust (RoT) with TPM 2.0 or platform firmware resilience requires dedicated secure processing elements on the PCB with isolated power and communication paths.

• Synchronization: Control plane servers do not require the nanosecond-level timing of the RAN, but microsecond-accurate time synchronization via NTP/PTP is essential for logging, charging, and lawful intercept functions.

2. Transport Network PCB Design

The 5G transport network connects base stations to each other (X2/Xn interfaces via midhaul) and to the core network (S1/NG interfaces via backhaul), as well as interconnecting core network functions. Transport network equipment spans a hierarchy from cell-site routers and switches to aggregation switches and core routers.

2.1 Cell-Site Transport PCB

Cell-site transport equipment — typically a compact, hardened router or switch installed at the base station site — must operate in uncontrolled environments with extended temperature ranges (-40°C to +65°C) and limited space/power. The PCB for cell-site transport equipment must balance port density (typically 4–8 × 10/25 Gbps SFP28 ports plus 2 × 100 Gbps QSFP28 uplinks) with power consumption and thermal dissipation in a sealed, convection-cooled enclosure.

Industrial-temperature-rated components and extended-temperature PCB materials (high-Tg FR-4 or mid-loss materials rated to 170°C Tg) are essential. The PCB layout must account for the reduced airflow in sealed enclosures by providing adequate copper area for heat spreading and thermal via arrays under the highest-power components (switch ASIC, PHYs, power regulators).

2.2 Aggregation and Core Router PCBs

Aggregation and core routers represent the highest-performance PCB designs in the transport network. A modern core router line card processes multiple 400 Gbps ports (typically 36 × 400G QSFP-DD in a single slot) through a merchant silicon switch ASIC (Broadcom Jericho3, Cisco Silicon One, or Nokia FP5) to a multi-terabit backplane interconnect.

The PCB for a 400G line card is a masterpiece of high-speed digital design:

• Layer count: 26–34 layers, with 6–8 dedicated to high-speed SERDES routing (100G PAM4 lanes at 53.125 Gbps)

• Material: Ultra-low-loss laminates (Megtron 8, Isola Tachyon 100G, or Panasonic M8) with Df < 0.002 at 10 GHz and ultra-smooth copper (Rz < 1.5 µm)

• Backplane connector: High-density connectors (Samtec Flyover, Amphenol ExaMAX, or Molex Impel Plus) with integrated ground shielding between columns, capable of 56 Gbps PAM4 and migrating to 112 Gbps PAM4

• PDN design: Multi-phase voltage regulators delivering 200–400 amps at sub-1V core voltages, requiring dozens of power plane pairs with embedded planar capacitance or buried capacitance layers to meet the target impedance at the ASIC pins

3. Multi-Access Edge Computing (MEC) PCBs

MEC brings compute and storage resources to the edge of the network — physically close to the RAN — to support ultra-low-latency applications like autonomous driving, augmented reality, and industrial automation. MEC server PCBs must deliver data center-class processing in form factors suitable for deployment at base station sites, street cabinets, or enterprise premises.

MEC PCBs face a unique set of constraints compared to traditional data center servers:

• Form factor: Short-depth chassis (300–450 mm vs. 600–800 mm for data center servers) compatible with telecom equipment racks (ETSI 300 mm or 600 mm depth)

• Power envelope: Limited to 150–300W per node in passively cooled or edge-constrained environments, versus 500W+ in data center racks

• Hardware acceleration: Integration of FPGA or GPU accelerators (NVIDIA A2/L4, Intel Agilex, Xilinx Versal) for AI inference, video transcoding, and packet processing — adding high-speed PCIe Gen4/5 routing to the PCB

• Precise timing: IEEE 1588v2 PTP support with hardware timestamping for applications requiring distributed time synchronization across MEC nodes

4. Network Slicing Hardware Considerations

Network slicing — the creation of multiple logical networks on a shared physical infrastructure — is primarily a software function. However, it imposes hardware requirements on the underlying PCBs. A network slice for ultra-reliable low-latency communications (URLLC) may require dedicated, isolated processing resources to guarantee latency bounds, while a slice for enhanced mobile broadband (eMBB) may require dedicated accelerator resources for high-throughput packet processing.

On the PCB level, slice isolation is achieved through PCIe SR-IOV (Single Root I/O Virtualization) that exposes multiple virtual functions from a single physical accelerator, hardware QoS queues in the switch ASIC and SmartNIC that provide per-slice traffic scheduling, and resource partitioning in FPGA-based accelerators where separate logic regions are assigned to different slices with isolated memory spaces.

5. Manufacturing Considerations for Core and Transport PCBs

Core and transport network PCBs demand manufacturing capabilities at the forefront of PCB technology:

• Ultra-low-loss materials: Supply chain management for advanced laminates with lead times of 8–16 weeks

• High-aspect-ratio vias: Through-hole aspect ratios to 12:1, laser microvias to 1:1, supporting 30+ layer stackups in 3–4 mm finished thickness

• Back-drilling precision: Stub length control to ±50 µm for 56 Gbps and 112 Gbps PAM4 signaling

• Copper plating uniformity: Consistent plating thickness across high-aspect-ratio vias to ensure reliability through thermal cycling

• Signal integrity validation: Frequency-domain S-parameter measurements to 50+ GHz on test coupons for every panel, ensuring compliance with IEEE 802.3 and OIF-CEI channel specifications

Superb Tech's advanced PCB fabrication facility is qualified to manufacture core and transport network PCBs with the layer counts, materials, and signal integrity requirements that carrier-grade 5G infrastructure demands.