The 5G New Radio (NR) base station — known as the gNB (next-generation Node B) in 3GPP terminology — represents one of the most complex electronic systems ever deployed at scale. A single gNB integrates massive parallel processing, high-speed digital interconnects, precision RF circuitry, and sophisticated antenna arrays into equipment that must operate continuously for years in environments ranging from climate-controlled data centers to exposed rooftop installations. At the heart of every gNB lies an extensive collection of printed circuit boards that implement the distributed architecture connecting Baseband Units (BBU), Remote Radio Units (RRU), and Active Antenna Units (AAU). This article provides a comprehensive analysis of 5G base station PCB hardware, from the digital processing core to the antenna aperture.

1. The 5G Base Station Architecture: A PCB Perspective

Modern 5G base stations follow a disaggregated architecture defined by the O-RAN Alliance and 3GPP specifications. The traditional monolithic base station has been split into three functional units, each with distinct PCB requirements:

• Central Unit (CU): Handles non-real-time Layer 3 (RRC) and higher-layer processing. Typically implemented on standard server-grade hardware with PCIe-based accelerator cards, the CU PCB is essentially a high-performance computing platform with specialized FEC (Forward Error Correction) acceleration.

• Distributed Unit (DU): Handles real-time Layer 2 (MAC/RLC) and partial Layer 1 (high-PHY) processing. The DU PCB is a high-speed digital processing board built around FPGAs, custom ASICs, or specialized baseband processors with massive DDR4/DDR5 memory bandwidth and 25/50/100 Gbps Ethernet interfaces to the CU and RU.

• Radio Unit (RU): Handles the remaining Layer 1 (low-PHY) processing, digital beamforming, and the complete RF chain from digital bits to antenna elements. In the AAU configuration, the RU and antenna array are integrated into a single unit, placing the most demanding PCB requirements on this subsystem.

This article focuses primarily on the DU and RU/AAU PCBs, which pose the greatest challenges for PCB design and manufacturing.

2. Baseband Unit (BBU) / Distributed Unit PCB Design

The DU/BBU PCB is fundamentally a high-speed digital design challenge. A single DU board may process 16 or more 100 MHz 5G carriers simultaneously, requiring aggregate baseband throughput exceeding 100 Gbps. This processing load drives the PCB design in several directions.

2.1 Baseband Processor and Memory Interface

The baseband processor — whether an Intel FlexRAN-enabled Xeon, a Marvell Octeon Fusion, or a custom ASIC from Ericsson or Nokia — interfaces with high-bandwidth memory (HBM) or external DDR5 DRAM. The DDR5 interface, operating at 4800–6400 MT/s, imposes strict signal integrity requirements on the PCB:

• Impedance control: 40-ohm single-ended for address/command lines, 80-ohm differential for DQ/DQS strobes, maintained within ±5% across the memory channel

• Length matching: All signals within a byte lane must be matched within ±2 ps (approximately ±0.3 mm on typical PCB materials), with DQS strobes centered in the DQ valid window

• Crosstalk management: Far-end crosstalk (FEXT) must be kept below -30 dB at the DDR5 Nyquist frequency (2.4–3.2 GHz), typically requiring at least 2× trace spacing (center-to-center spacing ≥ 3 times trace width)

• Power integrity: The VDD and VDDQ rails must maintain ripple below ±22 mV under the dynamic load of burst read/write operations, requiring a low-impedance PDN with target impedance below 5 milliohms across the 100 kHz–100 MHz range

DU PCBs typically employ 18–26 layer stackups with multiple ground and power plane pairs to satisfy the PDN impedance requirements. The memory interface traces are routed on inner stripline layers to minimize crosstalk and provide uniform dielectric environment for consistent propagation velocity.

2.2 Fronthaul Interface: eCPRI and O-RAN Split 7.2

The interface between the DU and RU — the fronthaul — has evolved from the proprietary CPRI (Common Public Radio Interface) standard to the open eCPRI (enhanced CPRI) protocol over Ethernet. A typical eCPRI interface operates at 25 Gbps per link, with multiple links aggregated to support the required bandwidth.

The eCPRI interface on the DU PCB is implemented using 25G/50G SERDES lanes routed to SFP28/QSFP28 optical module connectors. At 25 Gbps NRZ signaling (Nyquist frequency 12.5 GHz), the PCB trace loss budget from the SERDES pins to the optical module is typically 8–10 dB at Nyquist. On Megtron 6 or equivalent low-loss materials, this allows trace lengths up to approximately 250 mm with standard copper foil. For longer reaches or higher data rates (50 Gbps PAM4), enhanced ultra-low-loss materials (Megtron 7, Isola Tachyon 100G) and ultra-smooth copper foils become necessary.

3. Active Antenna Unit (AAU) PCB Design

The AAU represents the most challenging PCB subsystem in the 5G base station. It integrates the RF transceiver chain, digital beamforming processor, antenna array, and power management into a single weatherproof enclosure mounted on towers, rooftops, or street furniture.

3.1 Massive MIMO Antenna Array PCB

A typical 5G massive MIMO AAU incorporates a 64T64R (64 transmit, 64 receive) antenna configuration — an 8×8 array of dual-polarized patch antenna elements. Each of the 64 antenna paths requires its own complete RF chain: PA, LNA, T/R switch or circulator, filter, and digital step attenuator/phase shifter. The PCB must route these 64 identical RF paths with phase and amplitude matching across all channels.

The antenna elements themselves are fabricated directly on the PCB as microstrip patch arrays, typically using a multi-layer construction: the patch elements on the top layer, a ground plane on layer 2 (with coupling apertures for aperture-coupled feed), the feed network on layer 3, and additional ground/power layers below. This "stacked patch" configuration can achieve 15–20% impedance bandwidth — sufficient to cover the 3.4–3.8 GHz n78 band popular for 5G deployments worldwide.

3.2 Beamforming ASIC and RF Front-End Integration

The beamforming function — controlling the relative phase and amplitude of each antenna element to steer the array beam — is implemented in dedicated beamformer ASICs that integrate 8 or 16 channels per chip. An 8×8 array requires 4–8 beamformer chips, each requiring dense RF and digital routing on the PCB. The phase control resolution is typically 5.625 degrees (6 bits), requiring precise phase matching across the PCB traces between the beamformer outputs and the antenna feed points.

At 3.5 GHz, the wavelength in the PCB substrate is approximately 42 mm (assuming effective Dk of 4.0). A 5-degree phase error corresponds to a path length difference of approximately 0.6 mm — a tolerance that the PCB fabrication process must maintain across all 64 channels. This is achieved through symmetric, radial layout topologies centered on the beamformer ICs, with all antenna feed traces having inherently equal length by design.

3.3 Thermal Management: The AAU's Defining Challenge

The AAU's thermal challenge stems from the concentration of 64 PAs in a compact, weather-sealed enclosure. Even with PA efficiencies of 45–50% (using GaN technology), a 64T64R AAU with 200 mW per channel (total 12.8W RF output) may dissipate 15–25 watts of heat in the PAs alone. Combined with beamformer and transceiver IC power, the total PCB-level power dissipation can reach 200–400 watts for a high-power macro AAU.

The AAU PCB thermal design typically employs a metal-core or metal-backed construction where the PCB is bonded to a thick aluminum heatsink that forms part of the enclosure. Thermal vias under each PA device conduct heat directly to this metal base. For the highest-power AAUs, liquid cooling may be employed, with coolant channels integrated into the aluminum baseplate. The PCB material must maintain stable electrical performance across the -40°C to +85°C (or higher) operating temperature range, with particular attention to the thermal coefficient of dielectric constant.

4. Fronthaul and Backhaul PCB Interfaces

In addition to the DU and AAU PCBs, 5G base station hardware includes a variety of interface cards that connect the base station to the transport network (backhaul) and to other base stations and the core network (midhaul). These interface PCBs handle 25/50/100 Gbps Ethernet, often with hardware-based security (IPsec/MACsec) and precise timing distribution (IEEE 1588v2 PTP, SyncE).

The interface PCBs are typically implemented as plug-in cards (SFP28, QSFP28, QSFP-DD, or CFP2 form factors) or mezzanine modules that attach to the DU or switch fabric board. The PCB design focuses on high-speed signal integrity for the SERDES lanes and clean power delivery for the optical module lasers and CDR (Clock and Data Recovery) circuits, which are sensitive to power supply noise.

5. Manufacturing 5G Base Station PCBs

5G base station PCB manufacturing demands capabilities that push the limits of commercial PCB fabrication. Key requirements include:

• Layer counts: 18–30 layers for DU boards, 12–20 layers for AAU RF/digital hybrid boards

• Materials: Ultra-low-loss laminates (Megtron 7, Tachyon 100G, Rogers 3003/4350B) with Df < 0.003 at 10 GHz

• Copper profile: Ultra-low-profile or rolled copper foils with Rz < 2 µm for mmWave and high-speed digital layers

• Registration: Layer-to-layer registration < ±50 µm for reliable via landing on 0.8 mm pitch BGA

• Back-drilling: Stub removal on high-speed signal vias with depth accuracy ±75 µm

• Impedance control: ±7% on high-speed digital, ±5% on RF traces, verified by TDR on every panel

• Thermal management: Thermal via arrays, embedded copper coins, and metal-core bonding

Superb Tech's 5G infrastructure PCB manufacturing line is equipped to handle these requirements with direct imaging, laser drilling, advanced lamination presses for hybrid material stacks, and comprehensive electrical testing including 4-wire Kelvin measurements and automated impedance verification.