The system core is the architectural foundation upon which all radar capabilities are built. It defines the processing topology, the data flow between subsystems, the hardware-software boundary, and the interface standards that enable modularity and scalability. As defense acquisition programs increasingly mandate modular open systems approaches (MOSA) and alignment with the Sensor Open Systems Architecture (SOSA) Technical Standard, radar system architects must balance openness with the performance optimization that defense applications demand. This article explores the key architectural decisions in modern radar system core design.

Modular Open Systems Approach (MOSA)

MOSA is both a technical philosophy and an acquisition mandate. Its core principle is that systems should be composed of modular, interchangeable components with well-defined, publicly available interfaces. For radar systems, MOSA enables technology refresh without complete redesign, fosters competition among subsystem suppliers, and allows capabilities to be incrementally upgraded over the system’s decades-long service life.

The practical implementation of MOSA in radar begins with interface definition. The system core is decomposed into functional modules — waveform generator, receiver processor, beamformer, tracker, display processor — each communicating through standardized interfaces. The SOSA Technical Standard defines hardware slots (3U and 6U VPX), backplane profiles (Ethernet, PCIe, RF over fiber), and software frameworks that provide a common vocabulary for system integration. Aligning with SOSA reduces integration risk and ensures interoperability with other platform subsystems.

Processing Fabric Topology

The processing fabric connects computing elements within the radar system core. For high-throughput front-end processing, a fabric based on high-speed serial links — 25–56 Gbps lanes aggregated into 100–400 Gbps pipes — moves data between ADCs, FPGAs, and GPUs. The topology is typically a fat-tree or mesh, providing multiple paths between any two nodes for both bandwidth aggregation and fault tolerance.

For control plane traffic, a separate, lower-bandwidth network (Gigabit Ethernet or PCIe) carries configuration commands, health telemetry, and mode control messages. This physical separation of data and control planes prevents bulk data transfers from interfering with time-critical control messages, a principle borrowed from telecommunications network architecture.

Hardware-Software Co-Design

The partitioning of functions between hardware (FPGA/ASIC) and software (CPU/GPU) is the central trade-off in radar system core design. Functions with fixed, high-throughput requirements — digital beamforming, pulse compression, Doppler FFT — are natural candidates for FPGA implementation, where deterministic, low-latency processing is achieved through custom datapaths. Functions that benefit from algorithmic flexibility — tracking, classification, display processing — are better suited to software running on general-purpose processors.

The boundary is not static. Software-defined radar concepts push more functionality into software, using high-level synthesis (HLS) to target FPGAs from C/C++ descriptions when acceleration is needed. This approach trades some efficiency for dramatically faster development and easier maintenance, aligning with the MOSA philosophy of technology transparency.

Scalability and Future-Proofing

The system core architecture must accommodate growth. Additional processing cards, memory, and I/O channels should be addable without architectural changes. Chassis with more VPX slots, backplanes with higher-speed fabrics, and software frameworks that scale across multiple chassis provide headroom for future capability insertion. The architecture should also anticipate the integration of AI/ML accelerators, quantum-resistant cryptography, and new sensing modalities that may become operational during the system’s service life.

A well-designed system core is invisible when it works — data flows, processing happens, and results appear. But the architectural decisions embedded in that core determine the radar’s ultimate performance ceiling, upgradeability, and total ownership cost across decades of operation.