Once the radar receiver has down-converted and digitized the RF echo signals, the raw digital data stream enters the signal processing chain — a series of computationally intensive algorithms that extract targets from noise, clutter, and interference. The signal and data processing PCBs that implement these algorithms must handle aggregate data rates of tens to hundreds of gigabits per second while maintaining deterministic latency measured in microseconds. This article covers the complete digital processing chain: pulse compression, Doppler filtering, CFAR detection, track formation, and the FPGA/GPU processing boards and high-speed interconnects that make it all possible.

1. Pulse Compression and Matched Filter Processing

Pulse compression reconciles the conflicting requirements of long-range detection (requiring high pulse energy with long pulses) and fine range resolution (requiring short pulses). By transmitting a frequency-modulated or phase-coded waveform and applying a matched filter on receive, the radar achieves the range resolution of a short pulse while using a long, high-energy pulse. The matched filter is typically implemented as a Finite Impulse Response (FIR) filter in an FPGA, with the filter length equal to the pulse compression ratio (PCR), typically 100 to 10,000.

1.1 FPGA Pulse Compression Engines

A modern FPGA (e.g., Xilinx Versal or Intel Agilex) can implement pulse compression in the frequency domain using FFT-based fast convolution, which is more efficient than time-domain FIR filtering for PCR > 64. The processing chain: FFT of the received signal → complex multiplication by the stored reference waveform spectrum → IFFT → magnitude detection. For a radar with 100 MHz instantaneous bandwidth, 200 MSPS complex sample rate, and 1,024-point FFT, the processing requires approximately 5 GMAC/s (giga multiply-accumulate operations per second) per receive channel, well within the capability of a single FPGA. The PCB challenge is feeding the FPGA with the high-speed ADC data: a 16-bit, dual-channel ADC running at 200 MSPS produces 0.8 GB/s of data per channel (I/Q), requiring multi-lane JESD204B/C interfaces at 10–16 Gbps per lane. Superb Tech's high-speed digital PCBs support 112 Gbps PAM4 signaling with <1e-15 BER, ensuring error-free ADC-to-FPGA data transfer.

1.2 Reference Waveform Storage and Management

The pulse compression reference waveform (the complex conjugate of the transmitted waveform's spectrum) must be stored in high-speed memory accessible by the FPGA. For adaptive waveforms that change pulse-to-pulse, the reference must be updated within the inter-pulse period (typically 10–100 µs). This requires DDR4/DDR5 SDRAM or HBM (High Bandwidth Memory) with >50 GB/s bandwidth. The memory interface PCB — typically a 72-bit wide DDR4 bus at 3,200 MT/s — must maintain tight timing margins (setup/hold times <30 ps) through length-matched trace groups (byte lanes matched to <5 mil) and controlled-impedance routing (40 Ω for DDR4). Superb Tech's high-speed digital fabrication achieves the layer-to-layer registration and impedance control required for reliable DDR4/DDR5 operation.

2. Doppler Processing and MTI Filtering

Moving Target Indication (MTI) and Doppler processing exploit the Doppler frequency shift of moving targets to separate them from stationary clutter. The processing is typically implemented as a bank of narrowband filters covering the Pulse Repetition Frequency (PRF) interval, using FFT-based Doppler filter banks.

2.1 Doppler Filter Bank FPGA Implementation

A coherent processing interval (CPI) of 64 to 1,024 pulses is typically used, corresponding to a 64 to 1,024-point FFT across the slow-time dimension. For a radar with 10,000 range bins and 256-pulse CPI, the Doppler processor must compute 10,000 separate 256-point FFTs — approximately 2.5 million FFT butterflies — within the CPI duration (typically 10–100 ms). The FPGA implementation uses a deeply pipelined FFT core with 4–16 parallel processing lanes. The data flow architecture on the FPGA board is critical: range samples arrive sequentially (fast-time), but the FFT operates across pulses (slow-time), requiring a corner-turn memory that transposes the data matrix. This corner-turn memory — typically implemented in DDR4 or QDR SRAM — must support simultaneous read and write with aggregate bandwidth exceeding 100 GB/s. The PCB must route the wide memory buses with minimal crosstalk and skew, demanding tight control of trace spacing and length matching.

2.2 Clutter Maps and Adaptive Filtering

Ground, sea, and weather clutter exhibit spatial and temporal correlation that can be exploited for adaptive filtering. Space-Time Adaptive Processing (STAP) — used in airborne radars to detect slow-moving targets against ground clutter — combines spatial (array element) and temporal (pulse-to-pulse) filtering. STAP requires the inversion of a space-time covariance matrix of size NK × NK (where N is the number of array elements and K is the number of pulses), which for a 16-element array with 32 pulses is a 512 × 512 matrix. The matrix inversion is computationally O(N³K³), demanding significant FPGA DSP resources or a GPU/CPU co-processor. The data transfer from the array receiver to the STAP processor — N × K complex samples per CPI — flows through high-speed serial links (typically 10–40 Gigabit Ethernet or PCIe Gen4/5) on the signal processing PCB backplane.

3. CFAR Detection and Threshold Processing

Constant False Alarm Rate (CFAR) detection adapts the detection threshold to the local noise and clutter environment, maintaining a constant probability of false alarm despite varying background levels. CFAR is implemented as a sliding window processor that compares each range-Doppler cell against the average of its surrounding cells.

3.1 CFAR FPGA Architecture

A Cell-Averaging CFAR (CA-CFAR) for a range-Doppler map of 1,000 range bins × 256 Doppler bins must compute 256,000 threshold comparisons per CPI. The CFAR window — typically 16–32 guard cells and 16–32 reference cells on each side — requires a delay line that stores the window of samples. In FPGA, this is implemented as a shift register chain or block RAM with read/write pointers. The arithmetic (summation, division, multiplication by threshold factor) is straightforward, but the data flow must maintain throughput of one threshold computation per clock cycle at 200–400 MHz. The FPGA board's power delivery must handle the dynamic current draw of the DSP-intensive CFAR processing, which can reach 50–100 A at the core voltage (0.85 V). Superb Tech's power delivery network design for FPGA processing boards uses a multi-phase voltage regulator with point-of-load placement and low-ESR decoupling capacitors to maintain <10 mV ripple under dynamic load.

3.2 OS-CFAR and Advanced Detection Algorithms

Ordered-Statistic CFAR (OS-CFAR) provides better performance in multi-target environments by using the k-th ordered sample from the reference window rather than the mean. The sorting operation required for OS-CFAR is more complex than CA-CFAR, typically implemented using a systolic array or sorting network in FPGA logic. For very large range-Doppler maps (e.g., 8,192 × 1,024 for high-resolution imaging radar), the CFAR processing alone may consume 50–80% of the FPGA's logic resources, requiring multiple FPGAs on the processing board with high-bandwidth inter-FPGA links (e.g., Aurora or Interlaken protocols over 28 Gbps transceivers).

4. Track Formation and Data Processing

While signal processing operates on raw radar data (range-Doppler maps, detection reports), data processing operates at the next level of abstraction — associating detections into tracks, estimating target kinematics, and classifying targets. This processing is typically performed on general-purpose CPUs or GPUs rather than FPGAs, due to the algorithmic complexity and lower data rates.

4.1 Multi-Sensor Track Fusion PCB Architecture

Modern defense systems fuse tracks from multiple sensors — radar, IFF, ESM, IRST, and off-board sources — using algorithms such as Joint Probabilistic Data Association (JPDA) or Multiple Hypothesis Tracking (MHT). The track fusion processor is typically a ruggedized single-board computer (SBC) or a VPX/OpenVPX module with a multi-core CPU (Intel Xeon D or ARM Cortex-A72) and an FPGA for sensor interface management. The VPX backplane PCB — the interconnect fabric connecting multiple processing modules — must support multi-gigabit serial links (PCIe Gen4 at 16 GT/s, 10/40/100 Gigabit Ethernet, and Aurora) with <1e-12 BER. Superb Tech's VPX backplane manufacturing uses ultra-low-loss materials (Megtron 7 or Tachyon 100G) and precision backdrilling to minimize via stub effects above 10 GHz, achieving the signal integrity required for 25 Gbps+ backplane operation.

4.2 GPU-Accelerated Radar Processing

GPUs are increasingly used for radar processing tasks that benefit from massive parallelism: SAR image formation, STAP, and AI-based target classification. A radar GPU processing board — typically a PCIe add-in card with an NVIDIA A100 or RTX-class GPU — must provide: PCIe Gen4/5 ×16 interface (32–64 GB/s), GPU-to-CPU data transfer via NVLink or PCIe peer-to-peer, and adequate thermal management for the 300–500 W GPU. The GPU board's PCB is a 16–22 layer design with a massive BGA breakout (the NVIDIA A100 has over 5,000 balls), requiring stacked microvias (2–3 levels) and via-in-pad technology. The power delivery for the GPU core (typically 0.8 V at >400 A) uses a multi-phase VRM with the inductors and MOSFETs placed on the PCB directly underneath or adjacent to the GPU package to minimize I²R losses.

5. High-Speed Interconnects and Backplane Design

The data flows between radar processing subsystems push the limits of PCB interconnect technology. The aggregate data rate from ADCs to FPGAs, between FPGAs, and from FPGAs to CPUs/GPUs can exceed 1 Tbps in a modern multi-channel radar.

5.1 100G+ Serial Links and Signal Integrity

For inter-board and inter-chassis connections, 100 Gigabit Ethernet (using 4 × 25 Gbps lanes or 2 × 50 Gbps PAM4 lanes) is the emerging standard. At 25 Gbps NRZ, the Nyquist frequency is 12.5 GHz, and the PCB trace's insertion loss must be <10 dB to ensure a open eye diagram without equalization. This requires: ultra-low-loss laminate (Df < 0.002 at 10 GHz), smooth copper foil (RMS roughness <1 µm to minimize skin-effect losses), and precise backdrilling to remove via stubs. Superb Tech achieves insertion loss of <0.6 dB/inch at 12.5 GHz on Megtron 7 with HVLP (Hyper Very Low Profile) copper, enabling 30-inch trace lengths for 25 Gbps signals across a large backplane.

5.2 Optical Interconnects and Co-Packaged Optics

For the highest data rates and longest distances (>1 meter), optical interconnects replace copper traces. Co-packaged optics (CPO) integrate the optical transceiver (laser, modulator, photodiode) directly onto the processing PCB, eliminating the lossy and bandwidth-limited electrical channel between the ASIC and a pluggable optical module. The CPO PCB must accommodate: the optical fiber attachment (typically a fiber array with 125 µm pitch aligned to the photonic IC), the high-speed electrical interface between the ASIC and the photonic IC (typically 50–100 Gbps PAM4 over <10 mm trace length), and the thermal management of the laser (which dissipates 0.5–1.0 W). Superb Tech is developing CPO PCB capabilities for next-generation radar processing systems requiring >1 Tbps per module.