An IC substrate — also called a package substrate — is the interface between a bare die and the board it mounts on. It fans the die's fine-pitch I/O out to a BGA or LGA footprint the PCB can accept, which pushes feature sizes roughly an order of magnitude below a standard PCB: pads at 50 µm, routing pitch at 40 µm, solder mask bridges at 50 µm.
Superb supports IC substrate and package substrate builds in BT (bismaleimide triazine) and high-Tg FR-4, with pattern features down to 50 µm pads and 40 µm routing pitch, connector finger centre pitch to 150 µm, and BGA pitch from 0.3 mm. Where routing density demands it, the same supply chain delivers HDI and ELIC build-ups up to 30 layers.
IC Substrate Capability Parameters
| Min Pad Diameter | 50 µm |
| Min Routing Pitch | 40 µm |
| Min Trace / Space | 0.05 mm (50 µm) |
| Solder Mask Bridge | 50 µm |
| Min Finger Centre Pitch | 150 µm |
| BGA Pitch | From 0.3 mm |
| Max Layer Count | Up to 30 layers — ELIC (Every Layer Interconnect) HDI build-up |
| Base Material | BT (bismaleimide triazine); high-Tg FR-4; halogen-free FR-4 |
| Rigid Material Portfolio | FR-4 (lead-free / halogen-free / mid-Tg / high-Tg), BT, high-speed & high-frequency laminates, polyimide, EMI-shielding laminates, high-thermal-conductivity / IMS (optional) |
| Surface Finishes | ENIG, ENEPIG, immersion silver, OSP, selective hard gold |
IC Substrate Materials
BT (Bismaleimide Triazine)
BT is the mainstream substrate dielectric. Against standard FR-4 it holds a higher glass transition temperature, absorbs less moisture, and keeps dimensions stable across the repeated lamination and reflow cycles a package sees — the reasons it became the default for BGA and CSP substrates. Substrate builds in BT are supported down to 50 µm pads and 50 µm solder mask bridges.
High-Tg FR-4
For packages that do not need BT's dielectric performance, high-Tg FR-4 with lead-free and halogen-free options covers cost-sensitive and mid-volume programs. Halogen-free grades matter where the end product has to meet restricted-substance requirements, and lead-free grades are standard for RoHS-bound assemblies.
Mixed & Build-Up Stackups
Package substrates increasingly mix dielectric systems in one stackup, and many designs need HDI rather than plain through-hole routing to escape a 0.3 mm BGA pitch. ELIC build-ups to 30 layers are available in the same supply chain, so the substrate and the board it mounts on can come from one qualification and one DFM review.
Fine-Feature Process Control
Pad & Pitch Control
A 50 µm pad on a 40 µm routing pitch leaves very little margin. Imaging resolution, plating thickness uniformity and layer-to-layer registration all have to hold at the same time — a registration drift that would be harmless on a standard PCB closes a 40 µm gap. Registration is verified by microsection, and impedance-critical nets are checked on TDR coupons.
Solder Mask Bridge
At 50 µm the solder mask web between adjacent pads is thin enough that mask process choice stops being cosmetic and starts driving yield. A bridged or lifted web produces solder bridging on a 0.3 mm-pitch BGA, which is a rework-level defect rather than a touch-up. The 50 µm bridge is held as a production capability, not a best-case number.
Finger Pitch for Connector Interfaces
Where a substrate or module interface routes to an edge connector or a probe card, finger centre pitch runs to 150 µm. That geometry is sensitive to copper thickness distribution and plating wrap, so finger zones are inspected separately from the routing area.
IC Substrate Applications
| Data Center & HPC | FPGA / SoC packages (Xilinx / AMD Kintex UltraScale+, Virtex, Altera Agilex), 100G / 400G SmartNIC, NVMe storage controllers |
| Telecom & Wireless | 5G RU / RRU modules, OTN line cards (SFP28 / QSFP28), mmWave 24–60 GHz, GaN / SiGe PA chains |
| Industrial Vision & Automation | Smart camera and vision sensor packages (CSP / BGA,<5> |
| Aerospace & Defense | Phased-array radar TRM (GaN MMIC, hermetic packaging), satellite payload modules (low outgassing) |
| AR / VR & Spatial Computing | WL-CSP for AR smart glasses, VR headset main boards (XR2 SoC, LPDDR5 PoP) |
| High-Speed Data | SerDes characterisation boards (56G / 112G PAM4), retimer / redriver evaluation boards (PCIe Gen4 / Gen5) |
Test & Inspection
| Electrical Test | Flying probe / dedicated fixture; minimum test pitch 0.2 mm |
| AOI / SPI | 3D AOI and 3D SPI on all boards |
| X-Ray | 2D + CT X-ray, BGA / QFN void analysis |
| ICT / Boundary Scan | ICT and flying probe test, boundary scan (JTAG) |
| Metrology | Microsection, hole-wall copper thickness, dielectric thickness measurement |
Quality & Standards Compliance
Substrate and PCB builds run under the same quality system: ISO 9001:2015 and ISO 14001, with IATF 16949 for automotive, ISO 13485 for medical, IPC Class 3 for high-reliability programs, and GJB 362C-2021 / GJB 9001C-2017 / QJ 831B-2011 for military and aerospace. Inspection follows IPC-6012E, IPC-A-600J and IPC-TM-650; high-frequency and mixed-dielectric stackups follow IPC-6018 and IPC-4103.
Every order gets a free DFM manufacturability review before production release — Gerber / ODB++ format and netlist verification, stackup and panelisation check, and a written finding list with coordinates and severity grades. Send your package drawings or Gerber to pcba@superb-tech.com.
