1. The Convergence of PCB and Packaging

The traditional boundary between "printed circuit board" and "semiconductor package" is dissolving. As AI chips grow to reticle-limit sizes (800mm²+ for NVIDIA H100/B200) and incorporate multiple chiplets with high-bandwidth memory, the substrate that connects the silicon to the outside world must achieve line/space resolutions, layer counts, and material properties that exceed conventional PCB capabilities by an order of magnitude.

This article explores three advanced substrate technologies at the heart of AI chip packaging: FCBGA (Flip-Chip Ball Grid Array), HDI (High-Density Interconnect) substrates for IC packaging, and SLP (Substrate-Like PCB). While these share a common ancestry with conventional PCBs, their fabrication processes, materials, and design rules place them firmly in the realm of semiconductor packaging.

2. FCBGA Substrates: The Workhorse of AI Packaging

2.1 What Is an FCBGA Substrate?

Flip-Chip BGA (FCBGA) is the dominant packaging technology for high-performance AI chips. Unlike wire-bond packages where the die faces up and connects via gold wires, FCBGA flips the die face-down onto a substrate, with thousands of solder bumps forming the electrical and mechanical connection. The substrate then fans out these connections to a larger BGA array on its bottom side that attaches to the PCB.

2.2 Layer Architecture

A modern FCBGA substrate for an AI accelerator (e.g., NVIDIA H100, AMD MI300X) typically comprises 14-20 layers organized in a build-up structure:

2.3 Core vs. Coreless Substrates

Traditional FCBGA substrates use a BT (bismaleimide-triazine) or glass-epoxy core (400-800μm thick) that provides mechanical rigidity and serves as the power/ground distribution layer. However, for the thinnest, highest-performance applications, coreless substrates eliminate the thick core entirely, instead using additional build-up layers to achieve the required layer count.

Coreless advantages:

• Thinner overall package (reducing thermal resistance and improving z-height)

• Finer through-via pitch (no large mechanical drill vias)

• Better electrical performance (shorter signal paths, lower inductance power delivery)

Coreless challenges:

• No rigid core to resist warpage—requires advanced material engineering and stress balancing

• More difficult handling during assembly (thin, flexible substrates)

3. HDI Substrates for IC Packaging

3.1 Packaging HDI vs. PCB HDI

While both use the acronym "HDI," IC packaging substrates differ fundamentally from PCB-level HDI:

3.2 Semi-Additive Process (SAP) & Modified SAP

Conventional PCB fabrication uses a subtractive process: start with full copper foil, etch away unwanted copper. This limits minimum trace width to roughly the copper thickness (18μm foil cannot reliably produce traces narrower than ~20μm due to undercut).

IC substrate fabrication uses semi-additive process (SAP) or modified semi-additive process (mSAP):

1. Deposit a thin seed layer of copper (0.2-0.5μm) by electroless plating or sputtering

2. Apply and pattern photoresist to define the desired circuit pattern

3. Electroplate copper into the patterned areas to the desired thickness

4. Strip the photoresist

5. Flash-etch to remove the seed layer between traces

SAP/mSAP enables 8μm line/space with nearly vertical sidewalls, far finer than subtractive etching.

4. SLP: Substrate-Like PCB Technology

4.1 The SLP Bridge

Substrate-Like PCB (SLP) sits at the boundary between advanced HDI PCB and IC substrate. Originated by Apple for the iPhone X main logic board, SLP uses mSAP processing on select build-up layers to achieve 25/25 to 30/30μm line/space—finer than conventional HDI but not as fine as full-up IC substrate.

4.2 SLP for AI Edge Devices

For edge AI applications—smartphones, AR/VR headsets, drones—SLP technology enables unprecedented PCB density without the cost of full IC packaging substrate. An SLP board for an edge AI processor might feature:

• Hybrid construction: mSAP layers (top 3-4 build-up layers with 25/25μm L/S) + conventional subtractive etching for deeper layers

• Total layer count: 10-14 layers with 2-3-2 or 3-4-3 build-up

• Blind microvias: Laser-drilled, 50-60μm diameter

• Material: Modified ABF or low-CTE prepreg with spread-glass fabric

4.3 Cost-Performance Trade-offs

SLP costs approximately 3-5× more than equivalent-layer-count conventional HDI, but 2-3× less than a full IC package substrate. For edge AI products where board area is the binding constraint, SLP's density advantage can eliminate the need for expensive interposer boards or additional connectors, actually reducing system cost.

5. ABF: The Dielectric That Changed Everything

5.1 What Is ABF?

Ajinomoto Build-up Film (ABF) is a dry-film dielectric material developed by Ajinomoto Fine-Techno Co. that has become the universal build-up dielectric for advanced IC substrates. Unlike liquid dielectrics or prepregs, ABF is a B-staged epoxy film with silica filler that is laminated onto the substrate under vacuum, then laser-drilled to form microvias.

5.2 ABF Generations

5.3 ABF Supply Constraints

ABF is effectively a single-source material (Ajinomoto controls ~90%+ of the market). During the 2020-2022 chip shortage, ABF supply was a critical bottleneck for AI and HPC chip production. This has spurred investment in alternative build-up dielectrics from Sekisui Chemical, Showa Denko, and others, though ABF remains dominant.

6. Organic vs. Silicon Interposers

6.1 The Interposer Decision

For AI chips integrating HBM (High Bandwidth Memory) alongside the compute die, an interposer is required to provide the ultra-fine pitch interconnects (40-55μm microbump pitch) between the multiple die. Two competing technologies exist:

6.2 When Organic Wins

For AI accelerators where the total interposer area exceeds the silicon reticle limit (~860mm² per reticle for EUV), organic interposers (or "CoWoS-R" in TSMC's terminology) become the only viable option. The NVIDIA H100's CoWoS-S interposer is near the reticle limit; future designs may require multi-reticle stitching (costly) or transition to organic interposers.

7. Chiplet Integration & Advanced Substrates

7.1 The Chiplet Imperative

Monolithic AI chips at reticle limit confront yield and cost walls. The response is chiplet-based architectures: disaggregating the monolithic die into smaller chiplets (compute tiles, I/O tiles, memory controllers) that are interconnected on a common substrate. Examples include AMD's MI300X, Intel's Gaudi 3, and NVIDIA's future "die-disaggregated" designs.

7.2 Substrate Requirements for Chiplets

Chiplet integration places unprecedented demands on the substrate:

• Die-to-die interconnect density: UCIe (Universal Chiplet Interconnect Express) standard requires 45-55μm bump pitch with thousands of connections between chiplets

• Signal integrity: Die-to-die links operate at 16-32 Gbps per lane with tight BER requirements (<1e-27)<>

• Multi-die placement: Substrate must accommodate 4-12 separate die with ±5μm placement accuracy during chip-attach

• Warpage: Multiple die on a large substrate create complex, asymmetric stress patterns that drive warpage

7.3 Embedded Bridge Technology

For the densest die-to-die connections, embedded silicon bridges (e.g., Intel EMIB, TSMC LSI) embed tiny silicon interconnect chips within the organic substrate. The substrate itself is fabricated with cavities that house the bridges, enabling local ultra-fine-pitch connections without requiring a full silicon interposer. This hybrid approach combines the density of silicon interconnect with the cost and size advantages of organic substrates.

8. Copper Pillar & Microbump Interface

8.1 From Solder Bumps to Copper Pillars

The die-to-substrate interface has evolved from traditional C4 (controlled collapse chip connection) solder bumps to copper pillar bumps. A copper pillar consists of:

• Copper pillar (30-50μm height, 20-40μm diameter)

• Thin solder cap (5-15μm) on top of the pillar for bonding

• Under-bump metallization (UBM) on the die pad

Copper pillars enable finer pitch (down to 40μm vs. 130μm+ for C4) and better electrical/thermal performance than solder-only bumps.

8.2 Substrate Pad Design for Copper Pillars

The substrate must present precise landing pads for the copper pillar array:

• Solder mask defined (SMD) pads: Solder mask opening defines the pad area; provides better alignment tolerance

• Non-solder mask defined (NSMD) pads: Copper pad defines the connection area; better for fine pitch but requires tighter registration

• Surface finish: ENEPIG (electroless nickel, electroless palladium, immersion gold) is preferred for fine-pitch applications due to its flat surface and excellent wire-bond and solder compatibility

9. Warpage Control in Large Substrates

9.1 The Warpage Problem

Large FCBGA substrates (55mm × 55mm to 100mm × 100mm) with high layer counts experience complex warpage behavior during the multiple thermal cycles of assembly. A substrate that bows more than 80-100μm across its diagonal during reflow will cause non-wet opens or bridging defects. The root cause is CTE mismatch between the silicon die (2.6 ppm/°C), the substrate (12-16 ppm/°C for organic, 2.6 for silicon), and the PCB (14-18 ppm/°C).

9.2 Warpage Mitigation Strategies

• Balanced copper distribution: Dummy copper fills on sparse layers to equalize copper percentage across the stackup

• Low-CTE core: Using glass-cloth with low-CTE resin systems (XY CTE<10 ppm="">

• Symmetric build-up: Equal number of build-up layers on top and bottom of the core

• Stiffener rings: Metal stiffener rings bonded to the substrate perimeter to resist bending

• Lid attachment: The integrated heat spreader (IHS) or lid provides mechanical rigidity when bonded to the substrate

10. Future: Glass Core, RDL-First, and Panel-Level Packaging

10.1 Glass Core Substrates

Intel has announced plans to commercialize glass core substrates by 2026-2028. Glass offers:

• Near-zero CTE (0.5-1.0 ppm/°C vs. 12-16 for organic), virtually eliminating die-to-substrate CTE mismatch

• Atomically smooth surface enabling sub-1μm line/space by SAP

• Through-glass vias (TGV) using laser-induced deep etching, enabling 10:1 aspect ratios

• Excellent dimensional stability across temperature (critical for multi-die placement)

10.2 RDL-First Fan-Out Packaging

An alternative to traditional substrate-based packaging is RDL-first (Redistribution Layer-first) fan-out. This approach builds the interconnect layers directly on a temporary carrier using wafer-level processes, then attaches the die face-down. Key advantages:

• Finer L/S (2/2μm) using wafer stepper lithography

• No core needed—naturally coreless

• Smaller form factor (no substrate overhang beyond the die)

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10.3 Panel-Level Packaging

Panel-level packaging (PLP) migrates wafer-level processes to larger rectangular panels (510×410mm or 600×600mm), dramatically increasing throughput and reducing cost. PLP is the ultimate convergence of PCB panel processing and semiconductor lithography—and represents the future direction of advanced AI chip packaging.

11. Conclusion

The substrates that package AI chips—whether FCBGA, HDI, or SLP—are no longer simple "PCBs" in any meaningful sense. Their fabrication relies on semiconductor-grade lithography (SAP/mSAP), specialized dielectrics (ABF), and precision laser processing that exceeds conventional PCB manufacturing by an order of magnitude. As AI chips disaggregate into chiplets and incorporate silicon photonics, embedded bridges, and glass cores, the distinction between "substrate" and "interposer" will continue to blur.

For companies designing AI accelerators, understanding the full spectrum of substrate technologies—and their cost, performance, and supply chain trade-offs—is essential to making the right packaging choice. At Superb Automation, we track these developments closely and provide substrate solutions spanning from advanced HDI and SLP for edge AI to FCBGA-compatible integration platforms.