Modern UAV ISR payloads carry multiple cameras — EO (electro-optical), IR (infrared), and SWIR — each with its own video output format. The Video Interface PCB serves as the universal camera-to-processor bridge, accepting disparate video standards (MIPI CSI-2, HDMI, 3G-SDI, Camera Link, LVDS) and converting them to a unified format for the onboard image processor or video encoder. This board must handle aggregate video bandwidth exceeding 20 Gbps while maintaining frame-accurate synchronization across all cameras. Let's explore the high-speed interconnect design behind this aggregation platform.
Multi-Format Input Architecture
The video interface board provides physical connectors and signal conditioning for four primary camera interface standards:
MIPI CSI-2 (4-lane): Dominant in embedded cameras. Each 4-lane port supports 6 Gbps. A typical interface board hosts 3–4 MIPI inputs, implemented as 0.5 mm-pitch FPC connectors with 100 Ω differential routing to a CSI-2 aggregator (e.g., Toshiba TC358840 or Lattice CrossLink).
3G-SDI (SMPTE 424M): Broadcast-grade interface running at 2.97 Gbps over 75 Ω coax. The PCB uses 75 Ω controlled-impedance microstrip from the BNC connector to the SDI equalizer (LMH0394), with careful attention to the BNC launch geometry for return loss below -15 dB at 1.5 GHz.
HDMI 2.0: Consumer-grade interface at up to 18 Gbps across 4 TMDS lanes. Each TMDS pair requires 100 Ω differential impedance with intra-pair skew below 5 ps, necessitating strict length matching and a clean reference plane.
LVDS / Camera Link: Industrial machine-vision interface with 7:1 serialization. Multiple LVDS pairs (up to 10 per camera) route to an FPGA deserializer with source-synchronous clock forwarding.
SerDes Architecture for Long-Reach Cameras
In larger UAVs, cameras may be located 2–10 meters from the processing bay — far exceeding the practical length of MIPI or HDMI cables. The video interface PCB uses serializer/deserializer (SerDes) chipsets — notably the TI FPD-Link III (DS90UB953/954) or Maxim GMSL (MAX96705/MAX96706) — that tunnel video, control, and power over a single coaxial or STP cable at distances up to 15 meters.
On the PCB, each SerDes pair occupies a dedicated zone. The coax connector (FAKRA or mini-SMP) feeds a 50 Ω microstrip to the deserializer IC's input, with an AC-coupling capacitor (100 nF, 0201 package) placed within 2 mm of the IC pin. The parallel MIPI output from the deserializer to the aggregator is a 4-lane CSI-2 bus with 100 Ω differential routing.
Frame Synchronization Hardware
When multiple cameras must capture images simultaneously (e.g., for stereo depth or multi-spectral fusion), the video interface board distributes a hardware trigger signal to all cameras. This is implemented as a low-skew clock distribution network: a single LVCMOS trigger pulse from the host processor drives a 1:4 clock fanout buffer (CDCLVC1104), with each output trace length-matched to within 5 mm to achieve <1 ns frame synchronization across all cameras.
Power Distribution for Mixed-Voltage Interfaces
Camera interfaces span a wide voltage range: 1.8V (MIPI D-PHY), 2.5V (LVDS), and 3.3V (SDI/HDMI I/O). The interface board's power tree includes independent LDO rails for each voltage domain, with ferrite bead isolation between analog (video PLL) and digital (logic) supplies on the same rail. Total board power is typically 8–15W, managed through a 6-layer stackup with dedicated 3.3V and 1.8V power planes on inner layers.
Conclusion
The Video Interface PCB is the Rosetta Stone of UAV imaging payloads, translating between the diverse languages of modern camera interfaces and delivering synchronized, formatted video streams to the processing chain. Superb Tech manufactures video interface PCBs with multi-standard impedance control (50 Ω, 75 Ω, 100 Ω differential), SerDes coax routing, and precision trigger distribution.
