AAU Array Board PCBA

64T64R Active Antenna Unit for 5G Massive MIMO Base Station Deployments

Product Overview

The AAU Array Board PCBA is a high-density active antenna unit integration platform that combines 64 transmit and 64 receive channels on a single multi-layer PCB assembly for 5G massive MIMO base station deployments in the n77/n78 bands (3.3–3.8 GHz). Each channel integrates a GaN or LDMOS transmit power amplifier delivering 2–5 W per element, a GaAs receive LNA with sub-1 dB noise figure, a high-speed T/R switch, and a 6-bit digital step attenuator with 0.5 dB resolution — all within a footprint optimized for half-wavelength element spacing (approximately 42 mm at 3.5 GHz). Our HDI stack-up employs stacked microvias, buried vias, and buried capacitance layers to manage the extreme routing density required for 128 independent RF paths plus SPI digital control and distributed power delivery. The board includes integrated calibration couplers on every channel, enabling over-the-air array calibration without external test equipment — the coupler network feeds a corporate calibration combiner that allows end-to-end channel response measurement. Advanced thermal simulation verified through IR imaging that the distributed heatsink interface maintains junction temperatures below 105°C at full rated transmit power with 64 simultaneous channels active. Every AAU board undergoes automated channel-to-channel gain and phase characterization with statistical analysis of array uniformity. This PCBA serves as the RF foundation for next-generation 5G active antenna systems supporting beamforming, MU-MIMO, and full-dimensional MIMO (FD-MIMO).

Key Specifications

PCBA Assembly Challenges

AAU array assembly is among the most demanding in RF manufacturing. Each of the 64 channels contains a PA, LNA, T/R switch, and attenuator — typically in miniature QFN or LGA packages — placed within a 42 mm × 42 mm lattice. This density demands 0201 and 01005 passive components with placement accuracy of ±35 µm. The board undergoes multiple reflow passes: the bottom-side digital components are placed first at a lower peak temperature, followed by the top-side RF components at a full lead-free profile. The 14–20 layer board's thermal mass is substantial; reflow profiling must ensure that the PA packages' large exposed pads reach full liquidus temperature (above 235°C for SAC305) while preventing the adjacent LNA — rated for a maximum of 260°C — from exceeding its thermal limit. Solder paste volume on the PA's RF input/output pads is critical: insufficient volume causes RF performance degradation, while excess solder creates shorts under the 0.4 mm pitch QFN. Every board undergoes 3D X-ray inspection focused on BGA/QFN void rates under all active RF components, with void criteria below 15% per IPC Class 3 on all thermal and RF pads. The calibration coupler network's thin-film resistors must be placed with ±25 µm accuracy to maintain coupling factor uniformity across all 64 channels.

Test Strategy

AAU testing is a multi-stage automated process. Stage 1 verifies the digital infrastructure: SPI communication to all 64 channel controllers, power supply rails within ±3% at full load, and no short circuits on any of the 128 RF paths. Stage 2 characterizes each channel individually using a calibrated VNA with an automated RF probe station that steps through all 64 channels. For each channel, S-parameters are measured in both Tx and Rx modes: gain, input/output return loss, noise figure (Rx), output power at P1dB (Tx), and attenuation accuracy across all 64 states of the digital step attenuator. Stage 3 measures channel-to-channel uniformity by computing the gain and phase statistics across all 64 channels and flagging any channel exceeding the ±0.3 dB gain or ±3° phase window. Stage 4 is a thermal validation: all 64 Tx channels are activated simultaneously at rated power while an IR camera monitors the board surface; any channel exceeding 105°C junction temperature is flagged for heatsink interface rework. A final over-the-air test using the integrated calibration couplers verifies end-to-end channel response in both Tx and Rx paths.

PCB Manufacturing Difficulty

Fabricating the bare AAU PCB pushes the limits of HDI technology. The 14–20 layer stack-up combines high-speed digital layers (Megtron 6, for FPGA-to-transceiver routing) with RF layers (Rogers 4350B, for the antenna feed network and PA/LNA matching). This hybrid construction requires precision lamination with matched CTE to prevent warpage exceeding 0.5% across the panel — warpage creates coplanarity issues during SMT that cause opens on the large BGA packages. Each of the 64 element positions includes stacked microvias (layer 1-to-2, 2-to-3) for RF grounding, with backdrilled through-vias for the digital routing. The antenna-side ground plane must be continuous under the entire array with no splits or slots — any gap becomes a radiating element that corrupts the array pattern. The 128 RF traces from the beamformer ICs to the antenna elements are length-matched to ±2 mil using serpentine routing on inner layers, with full-wave 3D EM simulation used to verify that the serpentine sections do not create unintended coupling. Every panel includes TDR coupons for impedance verification of the RF traces and cross-section coupons to confirm layer-to-layer registration within ±2 mil.

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