High-Speed Router Backplane: Switch Fabric, SerDes & Multi-Terabit Architecture

Published June 21, 2026 • 7 min read • Telecom Insights

The high-speed router backplane is the central interconnect fabric that connects line cards, switch fabric cards, and route processor cards within a chassis-based router. In a multi-terabit core router, the backplane carries terabits per second of traffic across hundreds of differential signal pairs at 25–112 Gbps per lane — making it one of the most challenging high-speed digital designs in all of electronics.

Key Takeaway: A modern core router backplane (e.g., Cisco 8000, Nokia 7750 SR, Juniper PTX) carries over 200 Tbps of aggregate bandwidth across 1000+ differential pairs — each operating at 56–112 Gbps PAM4 — through PCB traces up to 1 metre in length. The signal integrity challenges at these speeds dwarf those of any other PCB design discipline.

Switch Fabric Architecture

The backplane's electrical design is inseparable from the switch fabric architecture it implements. Three generations define the evolution: Centralised fabric — dedicated switch fabric cards in the chassis interconnect all line cards via the backplane (traditional chassis model). Virtual Output Queueing (VOQ) — each line card has a VOQ per output port controlled by a central scheduler, eliminating head-of-line blocking. Distributed fabric — each line card integrates a fabric element; the backplane becomes a full mesh of high-speed links between all cards. Modern designs use a multi-stage Clos or Benes network with 3–5 stages in the fabric cards, providing non-blocking, any-to-any connectivity among line cards.

112G PAM4 SerDes Technology

The backplane's bit rate per differential pair has advanced from 10 Gbps (NRZ, ~2010) to 25 Gbps (NRZ) to 56 Gbps (PAM4) to the current 112 Gbps PAM4 generation. PAM4 (4-level Pulse Amplitude Modulation) encodes 2 bits per symbol, halving the Nyquist frequency to 28 GHz for 112 Gbps — critical for traversing PCB traces where loss at 56 GHz (required for NRZ) would be prohibitive. Key SerDes IP blocks: ADC-based receivers (64+ GSPS, 7–8 ENOB) with DSP-based equalisation (CTLE, DFE with 30+ taps), DAC-based transmitters with 3-tap FFE pre-emphasis, and forward error correction (FEC) — typically RS(544,514) for 56G and concatenated RS + KP4 for 112G. Power consumption is 5–8 pJ/bit for 112G PAM4 SerDes in 5 nm CMOS.

Orthogonal Backplane Connectors

The physical connector technology is as critical as the SerDes. Orthogonal connectors (Molex Impact, TE STRADA Whisper, Amphenol ExaMAX) mount line cards vertically on one side and fabric cards horizontally on the other — eliminating the midplane PCB entirely. This direct orthogonal connection avoids two connector interfaces + midplane traces, reducing loss by 6–10 dB at 28 GHz. Connector performance specifications at 112G: insertion loss <1 dB, return loss >15 dB, crosstalk <−50 dB (both NEXT and FEXT), and impedance tolerance ±5 Ω. The connector's footprint on the PCB is as carefully designed as the SerDes channel itself.

PCB Materials and Channel Design

Backplane PCB materials have evolved from standard FR-4 to ultra-low-loss laminates: Megtron 6 (Df ~0.002 at 10 GHz), Megtron 7 (Df ~0.001), and Tachyon 100G (Df ~0.0008). A typical backplane stackup uses 30–50 layers with back-drilled vias (minimum stub length <5 mils). Channel design at 112G requires full 3D electromagnetic simulation (HFSS, CST) of the entire end-to-end path — SerDes bump to connector to PCB to connector to SerDes bump. Key metrics: insertion loss <−30 dB at Nyquist (28 GHz for 112G PAM4), return loss >10 dB, integrated crosstalk noise (ICN) <1 mV RMS. Equalisation in the SerDes (TX FFE + RX CTLE + RX DFE) compensates for 30–35 dB of channel loss.

Multi-Chassis and Distributed Architectures

For capacities beyond a single chassis, multi-chassis fabric extension connects multiple chassis via optical inter-chassis links using CFP2/QSFP-DD coherent optics over single-mode fibre. The fabric operates as a single logical switch across all chassis. The emerging distributed chassis or disaggregated router model — separating line-card shelves from fabric-card shelves — allows independent scaling of port density and fabric capacity. This architecture, combined with SDN control and white-box hardware, is transforming the core router from a monolithic chassis into a composable, software-defined system aligned with 5G transport scalability requirements.

The router backplane represents the ultimate expression of high-speed digital and signal integrity engineering — where quantum effects in PCB dielectric materials and femtofarad-level parasitic capacitances determine multi-terabit system performance.