Co-packaged optics (CPO) represents a paradigm shift in data center interconnect — moving the optical engine from a pluggable module directly onto the switch or accelerator mainboard. By eliminating the electrical channel between the ASIC and the optical module, CPO reduces power consumption by 30–50% and enables bandwidth densities exceeding 1.6 Tbps per optical engine. The PCB that hosts these optical engines faces unique challenges beyond conventional high-speed design.

CPO Architecture: PIC + EIC + ASIC

A CPO implementation comprises three elements on a single PCB:

• PIC (Photonic Integrated Circuit): The silicon photonics die containing modulators, photodetectors, waveguides, and fiber couplers. Fabricated on SOI (Silicon-On-Insulator) wafers with 220 nm silicon waveguides.

• EIC (Electronic Integrated Circuit): The SerDes/analog die that drives the modulators and amplifies photodetector signals. Typically a 7nm/5nm CMOS chip mounted adjacent to the PIC.

• ASIC (Switch/GPU): The host compute die — connected to the EIC through ultra-short electrical traces on the CPO PCB.

PIC-to-EIC Interconnect: The Critical Path

The electrical path between PIC and EIC is the most sensitive interconnect on the entire PCB:

• Data rate: 112–224 Gbps PAM4 per lane. With 16 lanes per optical engine, total bandwidth reaches 1.8–3.6 Tbps per engine

• Trace length: Must be kept extremely short — ideally under 10 mm. At 224 Gbps PAM4 (112 Gbaud, 56 GHz Nyquist), even Megtron 7 has 1.5 dB/mm loss, consuming the entire link budget in ~20 dB

• Impedance: 100Ω differential ±5% — tighter tolerance than standard ±10% due to the minimal margin at these frequencies

• Termination: On-die termination at the EIC receiver; no external termination resistors (too much parasitic capacitance)

• Ground reference: Continuous, uninterrupted ground plane — any split or discontinuity creates an impedance spike that destroys the 56 GHz eye

Fiber Attach: Micro-Optical Alignment

Getting light from the PIC into optical fiber is a sub-micron alignment challenge on the PCB:

• Edge coupling: PIC waveguide edge polished and aligned to fiber array unit (FAU). Requires <0.5 μm X/Y alignment accuracy. Active alignment with UV-cured epoxy is standard.

• Grating coupling: Vertical grating couplers on PIC surface couple light to fibers positioned above the die. Less efficient (−3 to −5 dB per coupler) but easier to assemble.

• Fiber management: 16 fibers per engine × 8 engines per switch PCB = 128 fibers on a single board. Fiber routing, strain relief, and bend radius control (>30 mm minimum) consume significant PCB real estate

• Thermal stability: Fiber alignment must be maintained across 0–85°C. CTE-matched adhesives and mechanical fixtures are essential — a 1 μm shift can cause 1–2 dB of excess loss

PCB Material and Stackup Requirements

CPO PCBs demand extreme material performance for the PIC/EIC region:

• Ultra-low-loss: Megtron 8, Tachyon-100G, or PTFE-based laminates with Df <0.001 at 56 GHz. The difference between Df 0.001 and Df 0.002 is the difference between a 15 mm and 7.5 mm maximum trace — critical when components must be placed in close proximity

• Copper roughness: HVLP (Hyper Very Low Profile) copper with <1.5 μm RMS surface roughness. At 56 GHz, skin depth is 0.28 μm — the entire current flows in the roughness peaks, making surface profile the dominant loss mechanism

• Layer count: 20–28 layers typical. The PIC/EIC region may use a local high-performance core with different material than the rest of the board

• Mixed materials: PTFE (for ultra-low-loss signal layers) + Megtron (for power/distribution) in a single hybrid stackup. Lamination compatibility is a major manufacturing challenge

Power Delivery for Optical Engines

Optical engines require exceptionally clean power — modulator drivers and TIA (transimpedance amplifier) circuits are sensitive to power supply noise:

• Supply rails: Multiple isolated rails — 3.3V for control, 1.8V for analog, 0.9V for digital. Each with <5 mVpp ripple requirement

• PSRR: Modulator driver circuits have limited PSRR (20–30 dB). 10 mV of power supply ripple translates to 1 mV of signal degradation — potentially closing the eye

• LDO vs. switching: Low-noise LDO regulators for analog rails; switching regulators with extensive filtering for digital rails

• Star grounding: Separate analog and digital ground domains connected at a single point to prevent digital return currents from coupling into analog circuits

Manufacturing and Test

• Cleanliness: The fiber attach area requires Class 100 (ISO 5) cleanroom conditions. A single 1 μm dust particle on a waveguide facet causes significant optical loss

• Test: Beyond standard electrical test — each optical engine must be tested for insertion loss, return loss, and bit error rate (BER <10⁻¹⁵ for optical links) at both wafer probe and post-assembly stages

• Hermeticity: Some CPO designs require hermetic sealing of the PIC to prevent moisture-induced waveguide degradation over time