Edge AI inference — running models on devices at the network edge — demands a fundamentally different PCB design philosophy than data center accelerators. Power budgets of 5–20W, fanless thermal management, and compact form factors (often smaller than a credit card) create unique constraints. This article covers the PCB design strategies for edge AI core boards built around chips like NVIDIA Jetson Orin, Qualcomm QCS8550, and Hailo-8.

Edge AI SoC Comparison

HDI Stackup for Compact Edge AI Boards

Edge AI core boards typically use SOM (System-on-Module) form factors — 45 mm × 45 mm to 70 mm × 70 mm — with 260-400 pin board-to-board connectors. The constrained area forces HDI design:

• 8-layer Type II HDI (1-6-1): Suitable for 0.5 mm BGA pitch. Laser microvias on L1-L2 and L7-L8. Mechanical buried vias L2-L7. Cost-effective, good for Jetson Orin series.

• 10-layer Type III HDI (2-6-2): Required for 0.4 mm BGA. Stacked or staggered microvias L1→L2→L3. Moderate cost premium (~2× 8-layer).

• 12-14 layer Any-Layer HDI: Required for 0.35 mm BGA (Qualcomm QCS8550). Every layer pair laser-drilled. Highest cost (~4× standard) but necessary for the densest packages.

Power Management: PMIC Selection and PDN

At 5–20W, edge AI boards use integrated PMICs rather than discrete multi-phase VRMs:

• PMIC selection: Multi-rail PMICs (e.g., NXP PCA9450 for i.MX, TI TPS6594 for Jacinto) provide 5–12 regulated rails from a single 3.7–5V input. Integrated LDOs for noise-sensitive analog rails.

• Efficiency: PMIC efficiency targets >90% across 1–100% load range. At 15W board power, 90% efficiency means 1.5W of PMIC heat — must be managed in a fanless enclosure

• Power sequencing: Edge AI SoCs have strict power-up/down sequencing requirements (typically 5–8 rails in specific order). PMICs provide integrated sequencing; discrete solutions add cost and risk

• PDN impedance: Target <10 mΩ up to 50 MHz. Achievable with 2 power-ground plane pairs plus on-board decoupling (100 μF bulk + 22 μF MLCC + 0.1 μF per power pin)

LPDDR5/x Routing for Edge AI

LPDDR5 at 6400 MT/s is the standard memory for edge AI. Routing considerations:

• Point-to-point: Single DRAM package (PoP or discrete) with fly-by topology not needed — simplifies routing vs. the multi-DIMM server case

• DQ/DQS groups: 16 DQ + 2 DQS per channel × 4 channels = 64 DQ + 8 DQS pairs. Each byte lane must be matched to ±1 ps within the group

• Impedance: 40Ω single-ended for DQ, 80Ω differential for DQS. Reference to solid GND plane with no splits

• Via count: Minimize to <2 vias per signal. Via stubs must be backdrilled for 6400 MT/s operation

Fanless Thermal Design

Edge AI boards typically operate in sealed, fanless enclosures at −40 to +85°C ambient. Thermal strategy:

• Heat spreading: 2 oz copper on all layers. Dedicated thermal planes (L2, L(N-1)) that extend beyond the SoC footprint to spread heat across the board area

• Thermal vias: 0.3 mm drill, 0.8 mm pitch grid under the SoC — 100+ vias connecting to internal copper planes

• Heatsink attachment: Board-to-enclosure thermal interface via thermal pads or gap fillers. PCB copper exposes to enclosure wall for conduction cooling

• Component placement: Hot components (SoC, PMIC, DRAM) placed on top side for direct heatsink contact. Temperature-sensitive components (crystal oscillators, sensors) placed away from heat sources

Cost Optimization for High Volume

Edge AI boards ship in millions. Design-for-cost is paramount:

• Minimize layers: 8-layer is the sweet spot — adequate for 0.5 mm BGA with Type II HDI

• Standard materials: Mid-loss FR-4 (IT-968, EM-891) instead of Megtron — edge AI signal speeds rarely exceed 16 Gbps

• Panel utilization: SOM form factors nest efficiently on 18"×24" panels. 70 mm × 45 mm boards achieve ~90% panel utilization

• Component count: Integrated PMICs replace 20+ discrete LDOs and DC-DC converters. PoP memory eliminates DRAM routing entirely