Chiplet Interconnect Substrate PCBA

Substrate-Like PCB (SLP) for Heterogeneous Chiplet Integration

Product Overview

The chiplet interconnect substrate PCBA is a substrate-like PCB (SLP) that serves as the integration platform for heterogeneous chiplet architectures, where multiple compute, memory, and I/O dies are assembled side-by-side on a common high-density substrate without requiring a full silicon interposer. Leveraging UCIe (Universal Chiplet Interconnect Express) die-to-die interfaces at 32 Gbps per lane, the substrate routes parallel and serial interconnects between chiplets with sub-8 µm line/space traces produced by mSAP (modified semi-additive process). Our manufacturing combines large-format panel processing (510×515 mm) with 8–14 ABF build-up layers on a low-CTE core, enabling cost-effective heterogeneous integration that avoids the expense and size limitations of a full silicon interposer while maintaining the signal density needed for wide parallel die-to-die buses. The substrate supports hybrid bonding pad arrays at 25–55 µm pitch for advanced 3D stacking, and incorporates embedded passives (resistors and capacitors) within the build-up layers to reduce surface component count. Deployed in Intel Ponte Vecchio, AMD MI300 series, and custom AI/HPC chiplet designs where disaggregated architecture enables yield optimization through smaller die, IP reuse across product generations, and rapid design iteration for evolving AI workloads.

Key Specifications

PCBA Assembly Challenges

Chiplet interconnect substrate assembly introduces the unique challenge of multi-die placement with die-to-die alignment requirements that far exceed conventional single-die packaging. Multiple chiplets — often from different foundries with slightly different bump metallurgies — must be placed on the same substrate with relative positional accuracy of ±2 µm between adjacent dies to maintain UCIe parallel bus timing closure. Each chiplet die has its own thermal profile during thermocompression bonding; the substrate experiences localized heating and cooling cycles that must be managed to avoid warpage-induced misalignment of previously placed dies. The hybrid bonding approach used for 25–55 µm pitch interconnect combines copper-to-copper direct bonding with dielectric-to-dielectric fusion bonding in a single room-temperature step followed by annealing — this requires atomically flat surfaces (roughness below 0.5 nm RMS) on both the substrate pads and the die bumps, achieved through chemical mechanical planarization (CMP) at the substrate level. Void-free underfill between chiplets is particularly challenging due to the narrow 10–20 µm gaps between adjacent dies; capillary underfill must flow through these gaps without trapping air, and the fillet must not climb the die sidewall and interfere with adjacent interconnects. Large-panel processing (510×515 mm) introduces panel-scale warpage management that must control flatness to within 50 µm across the full panel during all bonding operations.

Test Strategy

Testing a chiplet interconnect substrate spans multiple domains from bare substrate to fully populated assembly. The bare SLP undergoes 100% electrical probe testing with flying-probe or probe-card systems capable of resolving 6/8 µm features, verifying continuity and isolation across all build-up layers. After die placement but before underfill and overmold, the assembly is probed at each chiplet's boundary scan or test access port to verify die-to-substrate interconnect integrity while rework is still possible — a partially assembled substrate with one defective chiplet can be reworked by removing and replacing that individual die, a key economic advantage of the chiplet approach. After final assembly, powered functional testing validates UCIe link training and data integrity at 32 Gbps/lane across all die-to-die interfaces, with BER below 1e-15 and lane-to-lane skew within the UCIe specification. The completed multi-chiplet module undergoes system-level testing with representative workloads distributed across compute, memory, and I/O chiplets to validate inter-chiplet coherency protocols and power management handshakes. Reliability testing includes 1,000 thermal cycles (−55°C to +125°C) with in-situ resistance monitoring on daisy-chain structures between chiplets, and biased HAST to validate long-term dielectric integrity of the mSAP build-up layers under voltage and humidity stress.

PCB Manufacturing Difficulty

Fabricating a chiplet interconnect SLP balances the line/space demands of IC substrates with the panel-scale economics of PCB manufacturing. The 6/8 µm line/space capability is achieved through mSAP, where a thin electroless copper seed layer is patterned with 5 µm dry-film photoresist, electroplated to final thickness, and then flash-etched to remove the seed layer between traces — a process that requires precise etch uniformity across the 510×515 mm panel to avoid line width variation exceeding ±10%. Laser-drilled microvias of 25–30 µm diameter connect between build-up layers with ±5 µm layer-to-layer registration maintained by stepper alignment. The embedded passive layers — thin-film resistors (NiCr or TaN) and high-Dk planar capacitors — are integrated into the build-up sequence, requiring additional deposition, patterning, and etching steps that must be compatible with the ABF lamination thermal budget. CMP planarization of the top pads is essential for hybrid bonding compatibility, demanding a process that achieves sub-0.5 nm surface roughness while maintaining copper pad recess below 5 nm relative to the surrounding dielectric — any deviation creates voids in the copper-to-copper bond interface. Finished substrates are singulated from the 510×515 mm panel by precision dicing saws, and every substrate undergoes 100% AOI, electrical probe test, and laser warpage measurement at room temperature and simulated reflow temperature before release to assembly.

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