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High-Speed PCB Design: Signal Integrity & Impedance Control

2026-06-23
High-Speed PCB Design: Signal Integrity & Impedance Control

High-Speed PCB Design: Signal Integrity & Impedance Control

Essential principles for designing high-speed digital PCBs that maintain signal integrity at multi-gigabit data rates.

As data rates push beyond 25 Gbps into 112 Gbps PAM4 territory, PCB design becomes an RF engineering discipline. Every millimeter of trace, every via transition, every reference plane discontinuity affects signal quality. Superb Automation provides end-to-end high-speed PCB design with controlled impedance fabrication — 50 Ω single-ended and 100 Ω differential, verified by TDR measurement on every production panel with ±5% tolerance. Our team handles DDR4/DDR5 memory interfaces, PCIe Gen4/Gen5, 100G Ethernet, and other multi-gigabit protocols from schematic to production.

When Does a PCB Become "High-Speed"?

A PCB design is considered high-speed when signal rise times are fast enough that transmission line effects become significant. The rule of thumb: if the signal rise time is less than twice the propagation delay of the trace, you must treat the trace as a transmission line with controlled impedance.

For modern digital interfaces — DDR4/DDR5 memory, PCIe Gen4/Gen5, USB 3.2, and 100G Ethernet — signal rise times are measured in picoseconds. At these speeds, even a few millimeters of uncontrolled trace routing can cause signal reflections, ringing, and bit errors. What worked at 100 MHz will fail at 10 GHz.

DDR5
~50 ps rise time
PCIe Gen5
32 GT/s, ~16 ps edge
112G PAM4
~9 ps unit interval
100G Eth
4×25G NRZ lanes

Impedance Control: The Foundation of Signal Integrity

Controlled impedance means designing PCB traces to have a specific characteristic impedance — typically 50 Ω for single-ended signals and 100 Ω for differential pairs. Four factors determine impedance: trace width, copper thickness, dielectric thickness to the reference plane, and the dielectric constant (Dk) of the PCB material.

Microstrip

  • Trace on outer layer

  • Reference plane below

  • Faster signal propagation

  • More susceptible to EMI

  • Typical: 50 Ω single-ended

Stripline

  • Trace buried between two planes

  • Better shielding, less EMI

  • More consistent impedance

  • Requires ≥4 layers

  • Typical: 100 Ω differential

Superb Tolerance

  • ±5% impedance tolerance

  • TDR verified on every panel

  • 50 Ω / 85 Ω / 100 Ω

  • FR-4, Megtron, Rogers, PTFE

Differential Pair Routing

High-speed serial interfaces — PCIe, USB 3.x, HDMI, Ethernet — use differential signaling where two complementary signals are routed as a matched pair. The pair must maintain consistent spacing along its entire length. Variations in spacing change the differential impedance, creating reflections that degrade the signal eye.

Length matching within a differential pair is critical. For 10 Gbps signals, the length difference between the two traces should be less than 5 mils. For 25 Gbps and above, even tighter matching is required. Every via, bend, and layer transition must be accounted for in the length-matching budget.

Return Path & Reference Planes

Every signal requires a return path. At DC and low frequencies, the return current takes the path of least resistance. At high frequencies, it takes the path of least inductance — which is directly under the signal trace in the nearest reference plane.

Critical rule: Any discontinuity in the reference plane — a split, a gap, or a layer change without a nearby via for the return current — creates an impedance discontinuity that causes signal reflection and EMI. High-speed designs must maintain continuous, unbroken reference planes under all critical signal traces.


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