AI inference accelerators — NPUs, custom ASICs, and FPGA-based solutions — serve a different role than training GPUs. They prioritize TOPS/Watt efficiency, low latency, and cost-effectiveness over raw floating-point performance. The PCBs that carry these chips demand HDI (High-Density Interconnect) technology due to fine-pitch BGAs, high pin counts, and aggressive cost targets. This article examines the HDI PCB design strategies for inference accelerators.

Inference Accelerator Chip Landscape

The BGA pitch — especially at 0.35–0.40 mm — dictates the HDI stackup architecture. Standard through-hole vias cannot fit between these pads, mandating laser-drilled microvias.

HDI Stackup Architectures

For inference accelerator PCBs, three HDI classes are relevant:

Type II HDI (1-N-1): 10-12 Layers

• Laser microvias on L1-L2 and L(N-1)-L(N) only

• Buried vias connecting inner layers L2-L(N-1)

• Suitable for 0.50-0.65 mm BGA pitch

• Cost: ~1.5× standard PCB

Type III HDI (2-N-2): 14-16 Layers

• Stacked microvias: L1→L2→L3 and L(N)→L(N-1)→L(N-2)

• Staggered microvias (preferred over stacked for reliability)

• Suitable for 0.40-0.50 mm BGA pitch

• Cost: ~2.5× standard PCB

Any-Layer HDI: 14-18 Layers

• Every layer pair connected by laser microvias

• No mechanical drilled vias at all

• Required for 0.35 mm BGA pitch (e.g., Google TPU v5e)

• Cost: ~4× standard PCB

Microvia Design Rules

• Laser drill diameter: 75–100 μm (UV laser) or 100–125 μm (CO₂ laser with conformal mask)

• Capture pad: Drill + 100 μm (175–225 μm pad for 75 μm drill)

• Target pad: Drill + 75 μm minimum

• Dielectric thickness: 50–80 μm between layers connected by microvias (laser ablation depth limit)

• Aspect ratio: 1:1 maximum (equal depth to diameter) for reliable copper plating

• Stacked vs. staggered: Stacked microvias (via-on-via) reduce breakout area but stress the lower via during reflow. IPC-6016 Class 3 requires staggered configuration

BGA Breakout Strategies

For a 0.40 mm pitch BGA with 0.25 mm land pad diameter:

1. Via-in-pad: Microvia directly in the BGA pad. Requires copper-filled and planarized vias. Expensive but necessary for outer-row breakout at 0.35-0.40 mm pitch

2. Dog-bone fanout: Short trace from pad to adjacent via. Viable only for ≥0.50 mm pitch

3. Escape routing: 2.0-2.5 mil trace/space on outer layers. Typically 2 traces between pads at 0.50 mm, 1 trace at 0.40 mm, zero at 0.35 mm (must use via-in-pad exclusively)

Material Selection for HDI

HDI laminates must be thin, dimensionally stable, and laser-ablatable:

• Build-up film: Ajinomoto GX-13 or GX-T31 (ABF) — 15–35 μm cured thickness. Laser-ablatable with UV laser. Dk 3.3-3.5, Df 0.005-0.008 at 10 GHz

• Core material: IT-968G, Megtron 6, or EM-891 for the main core — chosen based on signal speed requirements

• CTE: Build-up films have higher CTE (40–60 ppm/°C below Tg) than FR-4 cores (12–15 ppm/°C). This CTE mismatch causes reliability concerns at elevated temperature — must be modeled

Power Distribution in HDI

HDI stackups with thin dielectrics between layers provide excellent power-to-ground plane capacitance — an inherent PDN advantage:

• Plane capacitance: With 50 μm dielectric between Vcore and GND planes, plane capacitance is ~1.2 nF/cm². For a 50 mm × 50 mm plane pair, that's 30 nF of distributed high-frequency capacitance

• Decoupling placement: 0201 MLCCs (0.1-1 μF) on the bottom side, directly under the BGA, connected through microvias to minimize inductance

• Via inductance: Microvias have ~0.05 nH inductance (vs. ~0.5 nH for a PTH), dramatically reducing PDN impedance at high frequencies

Cost Optimization Strategies

Inference accelerators are more cost-sensitive than training GPUs. Strategies to reduce HDI PCB cost:

• Minimize HDI layers: Use Type II (1-N-1) instead of Any-Layer wherever BGA pitch allows

• Larger BGA pitch: If chip selection allows, 0.50 mm pitch enables standard Type II HDI with dog-bone fanout — saving ~40% vs. Any-Layer

• Panel utilization: Inference cards are often smaller (PCIe half-length, half-height). Optimize panel nesting for yield

• Mixed stackup: Use premium materials only on outer build-up layers; standard FR-4 for inner core layers