The UAV Signal Processing PCB is the digital workhorse that ingests raw data from high-speed ADCs — sampling radar returns at 3 GSPS, SIGINT spectrum at 500 MHz instantaneous bandwidth, or multi-channel sonar at 192 kSPS — and performs real-time FFTs, matched filtering, digital beamforming, and target extraction on an FPGA or DSP fabric. This board class demands the highest performance digital interfaces (JESD204B/C at 12.5 Gbps per lane), massive FPGA resources (Xilinx Kintex UltraScale+ or Altera Agilex), and power delivery networks capable of supplying 30–80A at sub-1V core voltages with <10 mV ripple.
JESD204B High-Speed ADC Interface
JESD204B is the dominant interface for GSPS-class ADCs because it eliminates the parallel LVDS bus bottleneck — replacing dozens of pairs with 2–8 serial lanes at 6.25–12.5 Gbps each. On the signal processing PCB, JESD204B layout rules are among the most stringent:
Stripline routing: All JESD204B lanes are routed as stripline on inner layers, sandwiched between continuous ground planes. This provides superior shielding and consistent 100 Ω differential impedance.
Inter-pair skew: All lanes within a JESD204B link must be matched to within ±5 mils (approximately 0.8 ps at stripline velocity) to ensure deterministic latency alignment.
AC coupling capacitors: Placed at the receiver (FPGA) side of each lane, using 0201 100 nF capacitors with minimal pad-to-ground capacitance to avoid impedance discontinuity.
Via transitions: When the signal must transition layers, ground-return vias flank each differential via pair with a spacing equal to the via anti-pad diameter. The anti-pad itself is sized to maintain impedance through the transition — typically calculated with a 3D EM solver (Ansys HFSS).
FPGA Power Distribution Network
A Kintex UltraScale+ KU15P FPGA draws 50A peak current on its 0.85V core rail during heavy DSP workloads. The PDN for this rail must maintain DC voltage within ±3% at the FPGA balls despite 50A of transient current with di/dt exceeding 100 A/µs. The PCB achieves this through:
Multi-phase buck converter: A 6-phase controller (TI TPS53681 or Infineon IR35215) with 60A capacity, placed within 40 mm of the FPGA BGA. Each phase uses a 0.22 µH power inductor with DCR current sensing to balance phase currents within 5%.
Buried capacitance: The PCB stackup includes a ZBC (Z-axis Buried Capacitance) layer — a very thin (8–12 µm) dielectric between the VCCINT and GND planes — providing roughly 500 pF/in² of planar capacitance that filters mid-frequency (50–200 MHz) noise.
Decoupling capacitor network: A staggered array of MLCCs (100 nF, 1 µF, 10 µF, 47 µF) in decreasing distance from the FPGA, with the smallest values placed directly beneath the BGA on the bottom layer using via-in-pad connections.
DDR4 Memory Architecture
Signal processing workloads store large datasets (radar range-Doppler maps, spectral data cubes) in external DDR4 SDRAM. A typical signal processing FPGA connects to four 16-bit DDR4-2666 devices in a 64-bit bus configuration, requiring careful fly-by routing for address/command nets and point-to-point data byte lanes with ±5 mil intra-byte matching.
Clock Distribution & Jitter Budget
The JESD204B link requires a deterministic latency reference clock with sub-100 fs RMS phase jitter (12 kHz–20 MHz integration band). The clock source — typically an LMK04832 or HMC7044 jitter cleaner — distributes device clocks and SYSREF signals to the ADC and FPGA. Clock traces are 50 Ω single-ended or 100 Ω differential stripline, with all SYSREF traces matched to within ±1 mil of the corresponding device clock trace.
Conclusion
The UAV Signal Processing PCB is the most digitally demanding board class in the avionics portfolio, pushing FPGA PDN design, multi-gigabit serial routing, and DDR4 memory interfaces to their limits. Superb Tech manufactures these high-performance boards with 16+ layer stackups, buried capacitance layers, JESD204B stripline routing, and full PDN impedance verification.
