5G Mid-Haul Switch: Aggregation, Packet Processing & Network Slicing

Published June 21, 2026 • 7 min read • Telecom Insights

The 5G Mid-Haul Switch sits at the aggregation point between the fronthaul network (RU-to-DU) and the backhaul network (CU-to-5GC), providing the F1 interface transport between multiple DUs and a centralised CU. As 5G RAN architectures move toward centralised CU deployments serving dozens of distributed DU sites, the mid-haul network becomes the critical aggregation layer — and the switch at its core must handle multi-hundred-gigabit throughput with carrier-grade reliability and deterministic latency.

Key Takeaway: A single mid-haul switch may aggregate traffic from 50+ DU sites, each serving a 100 MHz 64T64R cell — resulting in aggregate throughput exceeding 1 Tbps. Managing this bandwidth while maintaining per-slice QoS demands enterprise/data-centre-class switching silicon deployed in a telecom environment.

F1 Interface Aggregation

The F1 interface between DU and CU comprises F1-C (control plane) using SCTP/IP and F1-U (user plane) using GTP-U tunnels. Total F1 bandwidth per DU depends on cell loading: a fully loaded 100 MHz 64T64R cell generates approximately 10–20 Gbps of downlink user-plane traffic on F1-U. The mid-haul switch must aggregate these flows from all connected DUs while maintaining traffic separation (per-slice, per-UE) and QoS differentiation. Link aggregation (LAG) bundles multiple 25/100GE links between the switch and the CU for resilience and capacity.

Timing-Aware Switching

The mid-haul switch must be PTP-aware (IEEE 1588v2), acting as either a Boundary Clock (BC) or Transparent Clock (TC). As a BC, the switch terminates PTP flows from the grandmaster and re-originates them toward DUs, correcting for its own residence time. As a TC, it timestamps PTP event messages at ingress and egress, inserting the residence time into the PTP correction field. SyncE (Synchronous Ethernet) support at the PHY level provides frequency synchronisation independent of PTP. The switch must achieve Class B accuracy (±50 ns from grandmaster) for 5G NR TDD phase alignment requirements.

Network Slicing: VLAN and VxLAN

The mid-haul switch implements network slicing through VLAN (802.1Q) or VxLAN (RFC 7348) segmentation. Each network slice — eMBB, URLLC, mMTC — is assigned dedicated VLAN/VNI identifiers with separate QoS policies. VxLAN is preferred for CU-DU connectivity across Layer 3 networks, encapsulating F1-U GTP tunnels within VxLAN tunnels that span multiple IP subnets. The switch's access control lists (ACLs) enforce slice isolation, preventing traffic leakage between slices. HQoS (Hierarchical QoS) enables per-slice, per-DU, and per-UE traffic shaping and policing.

High Availability and Carrier-Grade Design

Telecom switches require five-nines (99.999%) availability — less than 5.26 minutes downtime per year. Key HA features include: redundant power supplies (AC and DC options, hot-swappable), redundant fan trays with N+1 configuration, graceful restart for routing protocols (OSPF, BGP), NSR (Non-Stop Routing) for stateful failover between redundant control planes, and MC-LAG (Multi-Chassis Link Aggregation) for switch-level redundancy. G.8032 Ethernet Ring Protection Switching (ERPS) provides sub-50 ms failover in ring topologies common in metro fibre deployments.

Deep Buffering and Congestion Management

RAN traffic is notoriously bursty — MAC scheduler decisions create frame-level throughput peaks followed by idle periods. The mid-haul switch requires deep packet buffers (multi-gigabyte) to absorb these bursts without tail-drop. WRED (Weighted Random Early Detection) and ECN (Explicit Congestion Notification) manage congestion proactively. PFC (Priority Flow Control) — IEEE 802.1Qbb — provides lossless Ethernet for control-plane traffic, while user-plane traffic uses standard lossy forwarding.

The 5G mid-haul switch is a specialised breed — combining data centre-grade throughput with telecom-grade reliability, precise timing, and deep QoS capabilities. As RAN virtualisation advances, these switches increasingly incorporate compute capabilities (DPU/SmartNIC) for in-line F1 processing and security functions.