RF Power Amplifier Board PCBA

GaN-on-SiC Doherty Power Amplifier — 4–6 Layer Heavy-Copper PCB for 5G NR Massive MIMO Base Stations

Product Overview

The RF power amplifier board PCBA leverages gallium-nitride-on-silicon-carbide (GaN-on-SiC) HEMT transistor technology to achieve the power-added efficiency (PAE) and linearity required by modern 5G NR base stations. Configured in a Doherty architecture, the board combines a Class-AB carrier amplifier with a Class-C peaking amplifier through a precision quarter-wave impedance inverter fabricated directly on the PCB. This topology maintains 45–55% PAE at 6–8 dB output back-off — the operating point at which 5G OFDM signals spend most of their time — dramatically reducing the thermal load on the remote radio unit cooling system. Output power ranges from 10 W per channel for small-cell deployments to 100 W for macro-cell configurations across the 2.3–2.7 GHz and 3.3–3.8 GHz 5G NR bands. Integrated microstrip directional couplers sample forward and reverse power for digital predistortion (DPD) feedback, enabling compliance with 3GPP TS 38.104 ACLR and EVM transmitter specifications. The Rogers 5880 or Taconic RF-35 low-loss PTFE-ceramic laminate minimizes dielectric heating at high RF power levels, while the 2 oz or heavier copper layers handle the DC supply current without excessive I²R voltage drop.

Key Specifications

PCBA Assembly Challenges

Assembling a high-power GaN PA board pushes every aspect of the SMT process. The GaN HEMT transistor — typically a flange-mount or air-cavity ceramic package — can dissipate 50–100 W of heat during operation and requires direct solder attachment to a copper heat spreader or coin embedded in the PCB. The transistor gate and drain leads are attached with high-temperature solder (Sn95/Sb5 or Au80/Sn20, liquidus > 230 °C) to survive the operating junction temperature, while the remainder of the board uses SAC305 for standard SMT components — this demands a two-pass reflow process with sequentially decreasing peak temperatures. Coplanarity of the flange-mount package must be held within 1 mil relative to the PCB surface; any gap under the flange creates a thermal barrier that raises junction temperature and reduces reliability. The Doherty impedance inverter — a 35-ohm quarter-wave transmission line — is implemented as a precision microstrip trace whose width tolerance of ±0.5 mil directly affects the impedance transformation ratio and thus the PAE at back-off. Post-reflow, every transistor solder joint is inspected with 2D X-ray to verify complete wetting under the entire flange area, and void content is held below 10% across the gate and drain pads.

Test Strategy

The PA board undergoes a comprehensive RF power characterization protocol before shipment. DC testing first verifies that the gate bias sequencing circuitry applies negative gate voltage before positive drain voltage is enabled — a critical safety requirement for depletion-mode GaN HEMTs to prevent instantaneous thermal runaway. The drain supply is then ramped to the nominal 28 V or 48 V rail, and quiescent drain current is verified within ±10% of the design value. Small-signal S-parameters are measured on a VNA from 10 MHz to 8 GHz to confirm gain, input return loss, and reverse isolation. Large-signal characterization uses a vector network analyzer with load-pull capability to measure output power, gain compression, and PAE at the rated P3dB across the operating band. AM/AM and AM/PM distortion data is captured at multiple power levels to generate a DPD look-up table, which is validated by applying a 100 MHz 5G NR test waveform and confirming ACLR below -45 dBc after DPD correction. Final production testing includes a 48-hour burn-in at rated output power into a 3:1 VSWR mismatched load to screen for infant-mortality failures in the GaN transistor.

PCB Manufacturing Difficulty

Fabricating a high-power RF PA board to IPC-6012 Class 3 RF/microwave standards requires expertise in PTFE-based laminate processing. PTFE materials such as Rogers 5880 lack the rigidity of FR-4 and undergo cold flow (creep) under clamping pressure; the lamination cycle uses a specialized slow-ramp profile with plasma pre-treatment of the PTFE surface to activate it for bonding. Plated through-holes in the heavy-copper layers (2 oz or more) require a panel-plate-then-pattern-image process to achieve uniform via wall plating, since the copper thickness differential between the via barrel and the surface copper would otherwise cause over-etching of the via pads. The thermal management structure uses embedded copper coins — solid copper slugs press-fit or bonded into routed cavities under each GaN transistor — to provide a low thermal resistance path from the transistor flange to the heatsink. The coin-to-PCB interface must be planar within 0.5 mil to prevent gaps when the transistor is soldered. Impedance control on the Doherty combiner traces is verified on every panel using TDR, with a tolerance of ±7% on the 35-ohm inverter section to maintain the design's efficiency and bandwidth. Finished boards undergo 100% high-pot (HiPot) testing at 500 VDC to verify isolation between the drain supply rail and ground before release to assembly.

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