Published June 21, 2026 • 8 min read • Telecom Insights
The 5G Distributed Unit (DU) — or O-DU in O-RAN terminology — hosts the real-time processing functions of the 5G NR protocol stack: the physical layer (low-PHY and high-PHY), MAC, and RLC layers. The DU is the most latency-sensitive element in the disaggregated RAN, operating on strict sub-millisecond deadlines as defined by 5G NR's flexible numerology. Every scheduling decision, HARQ retransmission, and beam switch must be computed and applied within the slot duration (0.5 ms or less).
Key Takeaway: The DU's MAC scheduler makes approximately 500,000 scheduling decisions per second in a loaded 100 MHz 64T64R cell — allocating PRBs, MCS, rank, and beam to potentially hundreds of active UEs within the 0.5 ms slot boundary.
O-RAN Split 7.2 and Functional Decomposition
The O-RAN Alliance defines the 7.2x functional split between DU and RU. The DU (O-DU) retains: high-PHY functions — scrambling, modulation mapping, layer mapping, precoding, resource element mapping, and beamforming weight computation; low-PHY functions — IFFT/FFT and cyclic prefix insertion/removal; MAC layer — scheduling, HARQ, multiplexing, and random access; and RLC layer — segmentation, ARQ, and sequence numbering. The RU (O-RU) handles beamforming weight application, digital-to-analog conversion, and RF processing. The FAPI (Functional Application Platform Interface) defines the message exchange between MAC and PHY within the DU.
MAC Scheduler: The Brain of the DU
The MAC scheduler is the most algorithmically complex component in the DU. It must allocate physical resource blocks (PRBs) across users to maximise cell throughput while maintaining fairness and QoS. Modern schedulers implement proportional fair (PF) scheduling as a baseline, enhanced with QoS-aware weighting (priority-based on 5QI values), MU-MIMO pairing (selecting users with orthogonal spatial signatures for simultaneous transmission), and link adaptation (selecting MCS based on CQI reports and outer-loop adjustments). The scheduler runs every slot (0.5 ms for 30 kHz SCS), with a compute budget of approximately 100–200 µs on optimised hardware.
HARQ and Ultra-Reliable Low-Latency
5G NR supports asynchronous HARQ with up to 16 parallel processes per carrier. The DU must process HARQ ACK/NACK from the UE within the slot boundary and schedule retransmissions with the appropriate redundancy version (RV). For URLLC (Ultra-Reliable Low-Latency Communications), the DU supports pre-emption — puncturing ongoing eMBB transmissions to insert urgent URLLC data — requiring the scheduler to dynamically reallocate resources. The PDCP duplication feature (sending the same PDCP PDU over two independent RLC paths) adds further complexity to the DU's RLC layer.
FAPI Interface and L1-L2 Abstraction
The SCF FAPI (Small Cell Forum Functional API) defines the interface between the MAC (L2) and PHY (L1) within the DU. Key FAPI messages include: DL_TTI.request (MAC instructs PHY to transmit a slot with specified PRB allocation, MCS, precoding), UL_TTI.request (schedules uplink reception), RX_IND.indication (PHY delivers decoded transport blocks to MAC), and CRC.indication (per-transport-block CRC pass/fail). FAPI's P7 (physical) and P5 (logical) split options provide flexibility in L1 implementation — P7 with tightly integrated PHY for high performance, P5 with abstracted PHY for vendor interoperability.
Hardware Platform: x86, ARM, or FPGA Acceleration
The DU's real-time requirements drive the hardware platform choice. x86 servers (Intel Xeon with DPDK and real-time kernel patches) dominate virtualised DU (vDU) deployments, processing a 100 MHz 4T4R carrier per CPU core. FPGA SmartNICs (Intel N6000, Xilinx Alveo) offload L1 processing — FFT/IFFT, LDPC encode/decode, and rate matching — achieving 64T64R performance in a single PCIe card. ARM-based SoCs (Marvell Octeon, NXP Layerscape) offer a power-efficient middle ground for integrated small cell DUs. The trend is toward inline L1 acceleration where PCIe-attached accelerators process the entire L1 pipeline without CPU intervention.
The 5G DU sits at the intersection of real-time computing, wireless protocol engineering, and hardware acceleration — a domain where microsecond-level optimisations directly translate to Mbps of cell throughput and milliseconds of user-perceived latency.
