SXM GPU Carrier Board PCBA

22–30 Layer NVIDIA NVLink Full-Interconnect Carrier for SXM5/SXM6 GPUs

Product Overview

The SXM GPU carrier board PCBA is the high-density mezzanine substrate that houses NVIDIA SXM5 (H100/H200) and SXM6 (B200) GPU modules in HGX baseboards. The carrier routes 900 GB/s NVLink 4.0/5.0 bidirectional bandwidth per GPU through ultra-fine-pitch interposers and thousands of differential pairs. Our assembly process achieves sub-2.2 mil trace/space capability, laser-drilled microvias with 1:1 aspect ratio, and void-free BGA soldering for the GPU socket interface. The board incorporates power planes delivering up to 700 W per GPU with sub-milliohm DC resistance. Each carrier undergoes full boundary scan, TDR impedance verification, and thermal cycling qualification. Deployed in NVIDIA DGX H100, HGX H200, and GB200 NVL72 platforms worldwide.

Key Specifications

PCBA Assembly Challenges

The SXM carrier board represents the pinnacle of PCBA assembly complexity in the GPU ecosystem. The SXM socket interface — a high-density LGA or BGA connector array with thousands of contacts at sub-millimeter pitch — demands coplanarity better than 0.08 mm across the entire socket footprint. Solder paste deposition uses ultra-fine-pitch stencils (80–100 µm thickness) with nano-coated apertures to achieve consistent paste release on 2.0 mil pad geometries. The board's 22–30 layers of dense copper planes create massive thermal mass; reflow profiling must balance a peak temperature of 235–245°C with ramp rates of 1–2°C/sec to avoid thermal shock to the low-Dk laminate while ensuring complete wetting of all BGA balls. The NVLink interposer region — where hundreds of differential pairs converge at the GPU socket — is the most sensitive area; any solder bridging or insufficient wetting here results in a non-functional NVLink port. Multiple reflow passes are typical for double-sided assembly (VRMs on reverse), requiring a staged sequence with temperature-controlled bottom-side heating to prevent secondary reflow on the primary side. All hidden joints under the socket, interposer, and BGA packages are inspected with 3D X-ray laminography; void rates are held below 10% on all critical power and signal balls.

Test Strategy

SXM carrier board testing is among the most comprehensive in the industry. Bed-of-nails ICT verifies all passive component networks, power rail isolation, and socket pin continuity — custom fixtures with over 5,000 spring-loaded probes are required for full coverage. Boundary scan (JTAG 1149.6) is essential for testing the thousands of NVLink differential pairs that are inaccessible to physical probes; AC-coupled interconnect testing validates each lane at-speed using IEEE 1149.6 capabilities. Impedance verification by TDR confirms that every differential pair meets the 85 Ω or 100 Ω target within ±8% across all signal layers. Powered functional testing with a known-good GPU module validates NVLink port link training at full 900 GB/s bandwidth, running memory BIST on all HBM channels and checking PCIe Gen5 link integrity at 32 GT/s. Thermal qualification subjects the carrier to 1,000 thermal cycles between -40°C and +125°C with continuous electrical monitoring to identify any marginal interconnects. Final burn-in runs 48–72 hours with the GPU under sustained compute load to catch early-life failures.

PCB Manufacturing Difficulty

The SXM carrier PCB is one of the most difficult bare boards to manufacture in volume. At 22–30 layers of Megtron 7 or equivalent ultra-low-loss laminate, registration tolerance across all layers must stay within ±1.5 mil — tighter than the standard ±2 mil due to the 2.0 mil trace/space geometry in the NVLink breakout region. Laser-drilled microvias (75 µm diameter) are stacked in multiple layers under the GPU socket and interposer zones, requiring precise laser energy control to avoid over-drilling into underlying copper pads. Backdrilling removes unused via stubs from all high-speed signal vias, with residual stub length controlled to under 5 mil to eliminate resonances above 28 GHz. The aspect ratio of plated through-holes approaches 14:1 in 30-layer boards, demanding advanced pulse-reverse plating with specialized levelers to ensure uniform copper thickness from barrel wall to pad. Impedance control is modeled with 3D full-wave simulation and verified by TDR on coupon traces from every panel; the 2.0 mil line width leaves virtually zero margin for etch variation. All finished boards pass 100% automated optical inspection, flying probe electrical test, and cross-section analysis on sacrificial coupons before release to assembly.

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