14-Layer 6-Step HDI — High-Voltage Power Transformer Module

14-layer 6-step HDI · 70 μm heavy copper · PTFE+FR4 · 2.5 mm · AC withstand > 2000 V · ENIG · Layer offset < 30 μm · Stacked laser via · Build-to-print from Gerber

Product Specifications

14-Layer 6-Step HDI Stack-Up

• 6 sequential build-up steps — six lamination + laser drill + copper plate cycles

• Core stack: L3–L12 10-layer core with PTFE+FR-4 hybrid laminate

• Build-up Step 1: L2–L3 and L12–L13 blind via + plate

• Build-up Step 2: L1–L2 and L13–L14 blind via + plate

• Steps 3–6: Additional staggered and stacked blind vias for high-density interconnect

• All vias copper-filled — stacked via chain through multiple build-up layers

• 70 μm copper on every layer — heavy plating maintained through all 6 build-up cycles

High-Voltage Design — AC > 2,000 V

• PTFE + FR-4 hybrid laminate — PTFE for high-voltage insulation, FR-4 for structural rigidity

• AC withstand > 2,000 V — tested per IPC-TM-650 2.5.7, no breakdown or flashover

• Creepage distance control — trace-to-trace and trace-to-plane spacing designed for HV clearance

• Partial discharge resistant — void-free lamination, no air gaps in high-field regions

• 70 μm thick copper — high current capacity for transformer primary and secondary windings

• 2.5 mm board thickness — sufficient dielectric thickness for HV isolation between layers

70 μm Heavy Copper Throughout

• Inner layers: 70 μm (2 oz) — transformer winding traces, high-current bus

• Outer layers: 70 μm (2 oz) finished — component pads, power terminals

• Uniform copper across all 14 layers — balanced stack-up, no warpage from asymmetric copper

• Pulse-reverse plating — uniform thickness across high-aspect-ratio traces and vias

• Thermal conductivity — thick copper planes spread heat from transformer core losses

Registration Precision — ≤ 50 μm Any Layer

• Layer-to-layer offset < 30 μm — between adjacent layers

• Any-layer cumulative offset ≤ 50 μm — L1 to L14 total registration error

• 6-step process control — each lamination + drill cycle aligned to fiducial targets

• Laser Direct Imaging (LDI) — ± 15 μm per layer, X-ray alignment per build-up step

• Critical for HV isolation — misregistration can reduce creepage distance, compromise voltage rating

6-Step Stacked Via Technology

• Laser-drilled blind vias — UV laser, 75 μm via diameter through 50 μm dielectric

• Stacked via chain — L1→L2→L3→L4 direct copper path through four build-up layers

• Copper-filled + planarized — flat surface for next build-up step, via-in-pad capable

• Plasma desmear — PTFE via wall activation between each build-up cycle

• X-ray verification per step — stacked via alignment checked before next lamination

ENIG Surface Finish

• Ni 3–6 μm / Au 0.05–0.12 μm — IPC-4552 compliant

• Flat pad surface — coplanarity for power transistor and transformer component mounting

• Wire-bond compatible — gold wire bonding on ENIG pads for power die attachment

• Multiple reflow cycles — module assembly + customer board-level assembly

Manufacturing Notes

• Build-to-print from Gerber RS-274X — HV test coupon included on production panel

• Hi-pot test 100% — AC > 2,000 V, 60 s, per IPC-TM-650 on every board

• 100% flying probe electrical test — continuity + isolation, all nets

• 100% AOI — 2 μm resolution, all 14 layers

• X-ray per lot — stacked via alignment, copper filling void check

• Cross-section per lot — via plating, dielectric thickness, copper thickness, registration verification

• Lead-free RoHS compliant — ENIG, PTFE+FR-4 laminate, no lead