Recently, U.S. RF chip giant Qorvo published an invention patent (Application No.: 202511171615.5, Publication No.: CN 121727516 A), focusing on a self-biased, low-harmonic, high-efficiency inverse Class D RF power amplifier circuit system. This technology addresses key industry challenges in traditional Class D power amplifiers, such as high harmonic components, complex biasing control, and output power instability caused by load impedance variations. Designed for low-power, low-cost radio applications such as Zigbee, Bluetooth Low Energy (BLE), and Ultra-Wideband (UWB), the solution offers three core advantages: high efficiency, low harmonic distortion, and wide load adaptability. Additionally, it simplifies the external design of RF chips and reduces overall system cost.

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No. 1: Background of the Patent

In traditional RF power amplifiers, Class A, B, and AB amplifiers offer good linearity but suffer from low efficiency. While conventional Class D switching amplifiers achieve higher efficiency, they face a significant increase in third-order harmonic components. Additionally, in low-power wireless applications, dynamic changes in antenna impedance can easily cause output power fluctuations. Moreover, conventional biasing schemes struggle to maintain power control accuracy under variations in process, voltage, and temperature (PVT).

With a combination of an inverse Class D amplifier architecture, a self-biasing feedback loop, and a 33% duty-cycle signal design, Qorvo's patent achieves three major breakthroughs: high efficiency, low second- and third-order harmonics, and constant output power. At the same time, it significantly reduces off-chip filtering components, making it well-suited for low-power, miniaturized wireless communication devices.

No. 2: Core Circuit System Architecture

The power amplifier circuit system in this patent consists of two main parts: an inverse Class D power amplifier and a self-biasing circuit system. The overall architecture is fully differential, with an integrated RF transformer for balanced-to-unbalanced conversion. The overall circuit structure is shown in Figure 1.

1. Core Design of the Inverse Class D Power Amplifier

The inverse Class D amplifier forms the foundation for achieving high efficiency. It employs laterally diffused metal oxide semiconductor (LDMOS) switching power transistors as the core, combined with a cascode structure, an RF transformer, and signal shaping transistors to address switching efficiency, voltage isolation, and harmonic suppression:

l Coupling of Main Switching Transistors with Cascode Configuration: The core consists of two LDMOS switching transistors, M1 and M2, which are cascode-coupled with M3 and M4, respectively. This isolates the amplifier input from the high output voltage swing at the drain, preventing M3 and M4 from breaking down due to high voltage stress while simultaneously improving switching efficiency.

l Current Waveform Shaping: Transistors M5 and M6 are coupled between the sources of M3, M4 and ground. They operate at high speed to shape the current waveform into an approximately square wave, ensuring efficient RF power transmission for the inverse Class D amplifier.

l Integrated RF Transformer: The tapped input winding of transformer 16 is coupled to the drains of M1 and M2, while the output winding is coupled to the antenna and ground. A capacitor C1 is used in conjunction to achieve tuning, filtering, and impedance matching. Additionally, the transformer serves as a balanced-to-unbalanced converter (balun), directly suppressing second-order harmonics (H2).

l Skew Correction Driver: A transmission digital control amplifier 26 corrects timing mismatches in the RF input signal. The driver 24 provides the drive signal for the power amplifier, ensuring synchronization of switching actions and reducing signal distortion.

2. Self-Biasing Circuit System (Core Innovation)

The self-biasing circuit system is key to achieving power stability, harmonic control, and PVT adaptation. It consists of a TX-LDO (low dropout regulator), a current-mode digital-to-analog converter (I-DAC), a digital processor, and a current mirror feedback loop, forming a closed-loop gate bias voltage control:

l TX-LDO Regulator 30: Generates a controlled gate bias voltage vgate_pavgate_pa​ for M1 and M2. It also generates the power amplifier operating current IPAIPA​ (adjustable from 1 mA to 60 mA) and the supply voltage vdd_PAvdd_PA​ (adjustable from 1.2 V to 1.8 V). A voltage comparator 32 compares vdd_PAvdd_PA​ with an external reference voltage vref_pavref_pa​ to dynamically adjust the bias.

l Current Mirror and Feedback Current Scaling: The power amplifier current IPAIPA​ flows through PMOS transistor MP1. It is mirrored and scaled by MP2, MN1, and MN2 at a ratio of 1:200 to generate a feedback current. This feedback current is compared with a reference current generated by the I-DAC, serving as the basis for the TX-LDO to adjust the gate bias.

l 4-Bit Binary-Scaled I-DAC 34 (Figure 2): This is a 4-bit binary-scaled PMOS current source, with the most significant bit (MSB) employing a thermometer-coded 16× scaling structure. The feedback current adjustment range is from 2 μA to 512 μA. It receives a digital value from the digital processor to generate the reference current.

l Digital Processor 36: Receives real-time feedback of the gate bias voltage vgate_pavgate_pa​, generates a digital value via firmware/lookup table, and sends it to the I-DAC through a digital bus 38, enabling digitally programmable adjustment of the feedback current, thereby precisely controlling IPAIPA​ and the output power.

3. Self-Biasing Feedback Closed-Loop Logic

A closed self-biasing feedback loop is formed between the power amplifier and the self-biasing circuit. The core logic is as follows: the actual current from the antenna load is compared with the I-DAC reference current, and the gate bias voltage vgate_pavgate_pa​ is dynamically adjusted accordingly, thereby varying the power amplifier operating current IPAIPA​. This maintains a constant output power even when the antenna load impedance changes.

No. 3 Key Technical Design and Harmonic Suppression Principle

The patent's core approach to achieving low second- and third-order harmonics lies in the combination of a fully differential architecture and a 33.33% duty-cycle RF input signal, while also improving drain efficiency. The relevant waveforms and spectrum comparisons are shown in Figures 3–6:

Second-Order Harmonic (H2) Suppression: The amplifier adopts a fully differential architecture, in which the second-order harmonic components are in phase at the two differential outputs and are directly suppressed by the integrated RF transformer, eliminating the need for additional filtering components.

Third-Order Harmonic (H3) Suppression: Instead of using the conventional 50% duty-cycle square wave signal for inverse Class D amplifiers, a 33.33% duty-cycle RF input signal (Figure 5) is employed. This design does not significantly alter the power of the first-order harmonic (the desired signal) but substantially reduces the third-order harmonic component (Figure 6). At the same time, it reduces power dissipation during the conduction period of the switching transistors, significantly improving drain efficiency.

Comparative Advantage: The 50% duty-cycle signal exhibits higher third-order harmonic amplitude (Figure 4), whereas the 33.33% duty-cycle signal achieves substantial H3 attenuation while preserving the fundamental power. Moreover, the differential architecture enables complete H2 suppression by the transformer, ultimately achieving dual suppression of both H2 and H3 harmonics.

No. 4 Core Performance and Technical Advantages

Compared with conventional RF power amplifier architectures, the circuit system of this patent offers six core advantages, with excellent performance verified through experiments:

High Efficiency and Low Power Consumption: The inverse Class D switching architecture combined with the 33% duty-cycle design significantly improves drain efficiency and reduces current consumption, markedly extending battery life in wireless devices.

Extremely Low Harmonic Distortion: The fully differential architecture and integrated RF transformer suppress H2, while the 33.33% duty-cycle signal reduces H3, eliminating the need for additional off-chip filtering components and lowering system cost and size.

Adaptive Load Impedance: The self-biasing feedback loop adjusts output power in real time, maintaining constant output power even when the antenna load impedance varies (Figure 7 shows minimal output power fluctuation across different load resistances).

Strong PVT Adaptability: The I-DAC-based self-biasing architecture simplifies output power programming and effectively offsets performance drift caused by variations in process, voltage, and temperature.

Precise Power Control: The I-DAC supports feedback current adjustment from 2 μA to 512 μA, and the digital processor enables digital programming, allowing the power amplifier current IPAIPA​ to be precisely adjusted from 1 mA to 60 mA.

High Integration: The RF transformer, biasing circuit, and driver circuit are integrated into a single system, meeting the design requirements of miniaturized wireless communication devices.

5. Application Scenarios of the Circuit System

This power amplifier circuit system is not a standalone device but is integrated into the transmit circuit of a wireless communication device (Figure 9). It can be widely used in various devices supporting low-power, low-cost wireless communication. Key application scenarios include:

l Short-Range Wireless Communication Devices: Zigbee modules, Bluetooth Low Energy (BLE) devices, Near-Field Communication (NFC) devices;

l Ultra-Wideband (UWB) Devices: UWB ranging and positioning modules, with bandwidth supporting 3.1 GHz to 10.5 GHz (bandwidth > 500 MHz);

l Portable Smart Devices: Smartwatches, wristbands, wireless earphones, mobile terminals;

l Internet of Things (IoT) Nodes: Low-power sensors, IoT gateways, smart home control modules;

l Other RF Devices: Wireless Local Area Network (WLAN) devices, navigation equipment, RF access points (APs)

Summary

Qorvo's patent for this self-biased, low-harmonic, high-efficiency inverse Class D RF power amplifier represents a significant technological innovation for low-power, low-cost radio applications. Its core value lies in breaking the traditional trade-off in Class D amplifiers between high efficiency and low harmonics, while simultaneously addressing the issue of power instability caused by load impedance variations through the self-biasing feedback loop.