ADF4106-Based PLL Frequency Synthesizer

Introduction

The ADF4106 frequency synthesizer can be used to generate the local oscillator in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low-noise digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable counters A and B, and a dual-mode prescaler (P/P+1). Counters A (6-bit) and B (13-bit) work in conjunction with the dual-mode prescaler (P/P+1) to achieve an N-divider (N = BP + A). Additionally, the 14-bit reference divider (R-divider) allows the REFIN frequency at the PFD input to be set to a selectable value. When used with an external loop filter and voltage-controlled oscillator (VCO), it can form a complete phase-locked loop (PLL). With its extremely high bandwidth, many high-frequency systems can eliminate the need for frequency doublers, thereby simplifying the architecture and reducing costs.  

1. In the field of wireless communication, high-performance frequency sources are core components of communication equipment, radar, electronic reconnaissance and countermeasure devices, and precision measurement instruments. Modern communication systems impose increasingly stringent requirements on the accuracy, resolution, conversion time, and spectral purity of frequency sources, with superior performance achieved through frequency synthesis technology. The phase-locked loop (PLL) frequency synthesis technology discussed in this paper is based on the synchronization principle of PLLs, synthesizing a wide range of discrete frequencies from a high-accuracy, high-stability reference crystal oscillator. A PLL frequency synthesizer is a phase-locked device and a discrete-interval frequency signal generator with high frequency stability.

2. Basic principles of phase-locked loop frequency synthesizer

The phase-locked loop is the foundation of frequency synthesis technology. A phase-locked loop (PLL) typically consists of a phase detector (PD), a loop filter (LP), a voltage controlled oscillator (VCO), and a variable program frequency divider.

A phase-locked loop is a phase error control system that compares the phase difference between an input signal and the output signal of a voltage controlled oscillator, generating an error voltage corresponding to the phase difference between the two signals. The error voltage is processed to adjust the frequency (phase) of the voltage controlled oscillator. When the loop is locked, the frequency difference between the input signal and the output signal of the voltage controlled oscillator is zero, and the phase difference no longer changes with time. At this time, the error control voltage is a fixed value, and the output frequency of the voltage controlled oscillator is equal to the frequency of the input signal, that is, fo=fr. The characteristic of phase-locked loop makes it applicable in automatic frequency control to achieve precise frequency control. To obtain a certain control voltage when the loop is locked, the phase detector must have a non-zero output, that is, the loop must have a phase difference, which maintains the synchronization of the two signals and stabilizes the output signal frequency.

Phase detector, also known as comparator, compares the phase of the input signal with the output signal of the loop to generate an error control voltage; The loop filter filters out high-frequency components and noise in the error voltage to ensure the required performance of the loop and increase its stability; The oscillation frequency of the voltage controlled oscillator is controlled by the output voltage of the loop filter, causing the output signal frequency of the voltage controlled oscillator to approach the input signal frequency and reducing the phase difference between the two signals. The function of a variable program frequency divider is to divide the output frequency of a voltage controlled oscillator and compare it with a reference frequency in phase, thereby generating an error control voltage, which is used to adjust the phase of the voltage controlled oscillator.

A phase-locked loop locks a high stability reference oscillator (usually a crystal oscillator), and the loop is connected in series with a programmable frequency divider. By programming to change the division ratio R and N of the programmable frequency divider, a stable output of N/R times the reference frequency can be obtained. The relationship between the output frequency fo of the frequency synthesizer and the reference frequency fr of the crystal oscillator is:

Among them, R is the fixed frequency division ratio, N is the program (variable) frequency division ratio, fr is the reference frequency output by the crystal oscillator, and fo is the output frequency of the frequency synthesizer.

3.Design and Implementation of a phase-locked loop frequency synthesizer based on ADF4106

3.1 Introduction to the integrated phase-locked loop chip ADF4106

ADF4106 is the latest phase-locked loop chip produced by ADI in the United States. It is an integrated digital phase-locked loop frequency synthesizer chip with high frequency upper limit and good performance. It integrates various important components of the phase-locked loop frequency synthesizer in a small chip. With the reasonable combination of one or two integrated circuits and a small number of peripheral circuits, a complete low-noise, low-power, high stability and highly reliable frequency synthesizer can be formed. The design and application are simple and flexible, and it is easy to reduce the system volume.  

The integrated phase-locked loop chip ADF4106 has a high operating frequency, up to 6.0GHz, and is mainly used in wireless transmitters and receivers to provide local oscillator signals for up and down conversion. The chip is mainly composed of low-noise digital phase detector, precise charge pump, programmable reference frequency divider, programmable A and B counters, and dual-mode pre divider (P/P+1) and other components. The digital phase detector is used to compare the output phase of the R counter and the N counter, and then output an error voltage proportional to the phase error between the two. There is also a programmable delay unit inside the phase detector to control the width of the flip pulse. This flip pulse ensures that the transfer function of the phase detector has no dead zone, thus reducing phase noise and reference spurious. The precise charge pump uses programmable current settings to achieve output. The programmable reference frequency divider is actually a 14 bit R counter, mainly used to divide the external constant temperature crystal oscillator, with a division ratio range of 1 to 16383, in order to obtain the reference frequency. The programmable A and B counters, as well as the dual-mode prescaler (P/P+1), jointly achieve the main division ratio N (N=BP+A). The dual-mode prescaler (P/P+1) is also programmable, and there are several modes for the value of P: 8/9, 16/17, 32/33, 64/65.

The biggest feature of ADF4106 is its extremely high operating frequency, which simplifies the frequency doubling devices of many high-frequency systems, simplifies the system structure, and reduces power consumption and equipment costs. Therefore, it has been widely used in high-frequency circuit systems.

3.2 Application Examples of ADF4106

By using ADF4106 as the core, selecting an external voltage controlled oscillator suitable for application needs, and designing corresponding loop filters, a low-noise, low-power, and high stability frequency synthesizer can be constructed.

Figure 3 shows an application example of a frequency synthesizer in a certain transmitter, with a working frequency range of 5.4GHz to 5.8GHz. In this frequency synthesizer, an external high-precision and highly stable 10MHz reference clock is connected to the reference clock input terminal (REFin) of ADF4106 through a 50 Ω matching resistor. After passing through an internal reference frequency divider (excluding 10), a reference frequency interval of 1MHz is obtained. The output drive loop filter of the internal charge pump of ADF4106 adopts a third-order passive low-pass filter. The parameter settings are: phase margin φ p=45 °, phase detector sensitivity Kd=2.5mA, voltage controlled oscillator sensitivity K0=80MHz/V, loop bandwidth ω p=50Hz, reference frequency interval FREF=1MHz, reference frequency division ratio R=10, main frequency division ratio N=RFOUT/FREF=5800, and additional attenuation of the filter Atten=10dB.

According to the design principle of loop filters and the following formula, the time constant is defined as:

C1, C2, and R2 can be calculated and given nominal values: C1=100pF, C2=1.5nF, R2=4.3k Ω, R3=6.2k Ω, C3=20pF.

The output of the loop filter is used to drive the voltage controlled oscillator. Here, ZCOMM's V940ME03 is selected as the voltage controlled oscillator, which has a high oscillation frequency; The output of the voltage controlled oscillator is fed back to the RF input of ADF4106, forming a loop that drives the RF output. At the RFout end of V940ME03, a T-shaped circuit is added to the RF output end of the entire circuit and the RF input end of ADF4106, mainly used to provide impedance matching of 50 Ω.

The dual-mode prescaler operates in 32/33 mode and is controlled by a microcomputer serial port. In this example, the AT89C2051 microcontroller from ATMEL company is used for control. AT89C2051 is a low-voltage, high-performance 8-bit CMOS microcomputer with 2 kbyte Flash programmable erasable read-only memory (EEPROM). It is manufactured using ATMEL's high-density non-volatile storage technology and is compatible with the industrial standard MCS51 instruction set and pin structure. By combining universal CPL1 and Flash memory on a single chip, AT89C2051 becomes a powerful microcomputer. The bidirectional I/O ports P1.7, P1.6, and P1.5 of AT89C2051 are respectively connected to CLK, DATA, and LE of ADF4106 to achieve data control transmission to ADF4106. The external 12MHz quartz crystal and internal oscillator together form a complete oscillation signal generator, providing a clock for the single-chip microcomputer system. X25045 is a watchdog timer, whose main function is to provide an independent protection system for the microprocessor AT89C2051. When the system fails, after an optional timeout period, the X25045 watchdog will respond with a reset (RESET) signal; At the same time, as a voltage monitor, it can also protect the system from low voltage states. When VCC drops below the transition point, the system resets, and the reset is ensured until VCC returns and stabilizes.

The supply voltage VDD of ADF4106 is 3V, and the supply voltage VCC of Vp and VCO is 5V, both of which are powered by a voltage regulator block for output. It should be noted that VDD must not exceed Vp, otherwise it may damage the device.

In this example, indicators such as phase noise and spurious emissions have met the standards of ADF4106 as shown in Figure 4 of the design manual. The typical value of the measurement result is -81dBc for phase noise/ Hz@1kHz Stray noise is better than -62dBc.

4 Conclusion

Due to its application in many high-frequency systems, the frequency synthesizer designed with ADF4106 simplifies the frequency doubling device, simplifies the system structure, reduces power consumption and equipment costs. Therefore, it has been widely used in high-frequency circuit systems such as broadband wireless access, instrumentation, wireless local area networks, and radio frequency base stations.