128-Layer High-Speed Server PCB Solution

[Material] Core Material Selection

[Stackup] Stackup & Impedance Design

• Balanced symmetrical stackup – 24+ layers, prevents warpage/twist
• Critical signal layers – Adjacent to solid reference ground plane, forming stripline/microstrip structures
• Impedance control – 100Ω differential / 50Ω single-end, tolerance ≤ ±7% (≤ ±5% for critical links)
• Power-ground pairs – Tightly coupled, forming low-impedance PDN

[Routing] Layout & Routing Strategies

• Intra-pair skew – <0.6ps for 112G PAM4 critical paths
• Back-drill – Residual stub ≤6mil (≤0.15mm) to eliminate reflections
• Shield isolation – GSG coplanar waveguide; separate sensitive from aggressor nets
• BGA fan-out – Any-layer HDI for pitch <0.5mm to handle high I/O density

[PDN] Power Integrity

• Thick copper – PDN layers ≥3oz to reduce DC IR drop
• Multi-stage decoupling – Dense MLCC array (0402/0201) suppressing mid-high frequency noise
• Low loop inductance – Dense stitching vias (0.2mm pitch) between power and ground planes

[Thermal] Thermal Management

• Thermal microvia array – Copper-filled vias under BGA to conduct heat to inner copper planes
• Liquid cooling ready – Structural provision for cold-plate liquid cooling space & channels

[Simulation] Simulation & Test Assurance

• SI/PI Simulation – Ansys HFSS/SIwave, Keysight ADS – full-channel S-parameters, eye diagrams, ILD, COM evaluation; PDN AC impedance & DC IR drop analysis
• Electro-thermal co-simulation – Xpeedic Notus, coupling thermal stress with electrical performance
• Manufacturing & Test – Layer registration ≤ ±25μm, 100% TDR impedance test, flying probe, cross-section analysis; accelerated thermal cycle / thermal shock reliability validation

[Advantages] Solution Advantages