Logic IC, NAND, DRAM: In-depth Comparison of the Three Major Semiconductor Chip Manufacturing Processes

I. Overview
Logic chips (CPU/GPU/SoC, etc.), NAND Flash memory, and DRAM (Dynamic Random-Access Memory) are the three pillars of the semiconductor industry. All three are based on silicon and share fundamental CMOS process platforms such as photolithography, etching, thin-film deposition, and chemical mechanical polishing (CMP). However, they fundamentally differ in terms of device architecture, process flow, and scaling paths in their core functional areas.

Logic chips aim for lateral scaling down to atomic dimensions, relying on Extreme Ultraviolet (EUV) lithography and Gate-All-Around (GAA) transistors to achieve peak performance. NAND Flash expands capacity by vertically stacking over 200 layers of memory cells, with its core challenge lying in ultra-high aspect ratio (HAR) etching. DRAM sits between the two, requiring both the industry's tightest lithographic pitch and the fabrication of nanoscale, high-aspect-ratio storage capacitors.

This article provides a systematic comparative analysis of the manufacturing processes for these three types of chips from four dimensions: device structure, front-end-of-line (FEOL) processes, back-end-of-line (BEOL) processes, and future challenges.

Clarifying the Concept of CMOS
Before delving into the specific comparisons, it is necessary to clarify a concept that can easily cause confusion. CMOS (Complementary Metal-Oxide-Semiconductor) itself is not a term exclusive to any particular type of chip but rather a fundamental technology platform. It refers to a complementary structure that utilizes both NMOS and PMOS transistors.

Logic chips (CPUs, GPUs, SoCs, FPGAs, etc.) are entirely composed of standard CMOS transistors for computation and signal processing, representing the purest embodiment of CMOS technology. However, NAND Flash and DRAM also rely on CMOS. While their memory arrays use dedicated, non-standard device structures (e.g., charge-trapping cells, 1T1C memory cells), the peripheral circuits—such as read/write control circuits, sense amplifiers, and I/O drivers—are standard CMOS circuits. In 3D NAND, leading manufacturers even fabricate CMOS peripheral circuits beneath the memory array (CuA, or CMOS under Array), with both coexisting on the same chip.

Therefore, a more accurate understanding is that CMOS is the shared underlying language for all three. Logic chips, NAND Flash, and DRAM are three different applications built upon this language. The foundational manufacturing processes—photolithography, etching, thin-film deposition, CMP, ion implantation, etc.—are common among them. The core differences lie in the specialized device structures for the memory array sections and their corresponding unique process modules.

This article focuses on the core functional areas of each type of chip: the transistors in logic chips, the three-dimensional memory array in NAND Flash, and the access transistors and capacitors in DRAM, analyzing their systematic differences in manufacturing processes. The term "logic chips" or "logic ICs" is used herein to refer to chips primarily for computation (CPU/GPU/SoC, etc.), to avoid equating the CMOS technology platform with a specific chip type.

II. Device Structure Comparison: From Transistors to Memory Cells

Logic Chip Device Structure: Planar MOSFET → FinFET → GAA Nanosheet
The transistor architecture of logic chips has evolved through three generations. The planar MOSFET dominated from the 1960s up to the 22nm node, where the gate controls the channel current from only one surface. When the gate length shrank to approximately 25nm and below, short-channel effects (SCE)—including drain-induced barrier lowering (DIBL) and subthreshold leakage—became uncontrollable.

FinFET (Fin Field-Effect Transistor) addressed this issue by raising the channel into a vertical silicon fin, allowing the gate to wrap around the channel on three sides. Intel introduced the FinFET (Tri-Gate) process at the 22nm node in 2011. At advanced nodes (e.g., 5nm), the fin width is about 5–7nm, fin height about 45–50nm, fin pitch about 25–30nm, and contact poly pitch (CPP) has shrunk to approximately 48nm.

The current frontier is the Gate-All-Around (GAA) nanosheet transistor. Samsung began mass production of GAA process (MBCFET) at the 3nm node in 2022, while TSMC's N2 node introduced nanosheets in 2025. In GAA, the channel consists of 3–4 layers of horizontally stacked nanosheets (each about 5nm thick), with gate material completely surrounding each nanosheet from all four sides. A key process difference lies in epitaxially growing alternating Si/SiGe superlattices, followed by selectively etching away the SiGe layers to release the Si nanosheet channels. This channel release step has no equivalent in NAND and DRAM processes.

Future roadmaps include Fork-sheet transistors and Complementary FET (CFET), the latter vertically stacking NMOS and PMOS transistors to further shrink cell area.

NAND Flash Memory Device Structure: Floating Gate → Charge Trap → 3D NAND
NAND Flash stores data by trapping charge, which fundamentally differs from the switching transistors in logic chips. Early two-dimensional Floating Gate cells used a polysilicon floating gate, isolated between a tunnel oxide (about 8nm SiO₂) and an inter-poly dielectric (ONO stack: SiO₂/Si₃N₄/SiO₂), with a control gate on top. Electrons move in and out of the floating gate via Fowler-Nordheim tunneling, altering the cell's threshold voltage.

Charge Trap Flash (CTF) replaced the conductive floating gate with a Si₃N₄ charge-trapping layer. Since charges are confined to discrete sites within the insulating silicon nitride rather than freely distributed in a conductor, CTF offers stronger resistance to interference between adjacent cells, which is crucial for 3D stacking.

3D NAND revolutionized the architectural approach. Instead of shrinking lateral dimensions (2D NAND reached its physical limits at around 15nm), manufacturers began vertically depositing alternating oxide/nitride (O/N) layer pairs. Current mass production exceeds 200 layers, with the industry targeting 1,000 layers by 2030. Vertical channel holes are etched through the entire stack. The inner walls are sequentially deposited with a blocking oxide, a charge-trapping nitride layer, a tunnel oxide, and finally filled with polysilicon channel material. The sacrificial nitride layers are subsequently replaced with tungsten (W) or molybdenum (Mo) word lines during a gate replacement process.

逻辑IC,NAND,DRAM,半导体三大芯片制造工艺深度对比

一、概述

逻辑芯片（CPU/GPU/SoC等）、NAND Flash闪存和DRAM动态存储器是半导体产业的三大支柱。三者均以硅为基底，共享光刻（Photolithography）、刻蚀（Etching）、薄膜沉积（Deposition）和化学机械抛光（CMP）等CMOS基础工艺平台，但在核心功能区的器件架构、工艺流程和微缩路径上存在根本性差异。

逻辑芯片追求横向微缩至原子尺度，依赖EUV极紫外光刻和全环绕栅极（GAA）晶体管实现最高性能；NAND Flash通过纵向堆叠超过200层的存储单元进行容量扩展，其核心挑战在于超高深宽比（HAR）刻蚀；DRAM则处于二者之间，既需要业界最紧密的光刻间距，又必须制造纳米级高深宽比存储电容。

本文从器件结构、前道工序（FEOL）、后道工序（BEOL）和未来挑战四个维度，对三类芯片的制造工艺进行系统性对比分析。

关于CMOS的概念澄清

在进入具体对比之前，有必要先厘清一个容易引起混淆的概念。CMOS（Complementary Metal-Oxide-Semiconductor，互补金属氧化物半导体）本身并非某一类芯片的专属名词，而是一种基础技术平台，指的是同时使用NMOS和PMOS晶体管的互补结构方式。

逻辑芯片（CPU、GPU、SoC、FPGA等）全芯片均由标准CMOS晶体管构成，用于计算和信号处理，是CMOS技术最纯粹的体现。但NAND Flash和DRAM同样离不开CMOS。它们的存储阵列虽然使用了专用的非标准器件结构（电荷俘获单元、1T1C存储单元），但外围的读写控制电路、感测放大器、I/O驱动等均是标准CMOS电路。在3D NAND中，领先厂商甚至将CMOS外围电路制造在存储阵列的下方（CuA，即阵列下CMOS），二者共存于同一颗芯片中。

因此，更准确的理解是：CMOS是三者共同的底层语言。逻辑芯片、NAND Flash和DRAM是在这套语言上构建的三种不同应用。基础制造工艺（光刻、刻蚀、薄膜沉积、CMP、离子注入等）在三者间是共通的，核心差异体现在存储阵列部分的专用器件结构和相应的特有工艺模块上。 

本文重点聚焦于三类芯片各自的核心功能区，即逻辑芯片中的晶体管、NAND Flash中的三维存储阵列、DRAM中的存取管与电容，分析它们在制造工艺上的系统性差异。本文使用"逻辑芯片"或"逻辑IC"指代以运算为主的芯片（CPU/GPU/SoC等），以避免将CMOS技术平台与某一类芯片画等号。

二、器件结构对比：从晶体管到存储单元

 逻辑芯片器件结构：平面MOSFET → FinFET → GAA纳米片

逻辑芯片的晶体管架构经历了三代演进。平面MOSFET自1960年代起主导至22nm节点，栅极仅从一个表面控制沟道电流。当栅极长度缩至约25nm以下时，短沟道效应（SCE），包括漏致势垒降低（DIBL）和亚阈值漏电，变得不可控制。

FinFET（鳍式场效应晶体管）通过将沟道拉伸为竖直的硅鳍片来解决此问题，栅极从三个侧面环绕沟道。Intel在2011年的22nm节点率先引入FinFET（Tri-Gate）工艺。在先进节点（如5nm），鳍片宽度约5~7nm，鳍片高度约45~50nm，鳍片间距约25~30nm，接触多晶硅间距（CPP）收缩至约48nm。

当前前沿是全环绕栅极（GAA）纳米片晶体管。Samsung于2022年在3nm节点量产GAA工艺（MBCFET），TSMC的N2节点于2025年导入纳米片。GAA中，沟道由垂直堆叠的3~4层水平纳米片组成（每层约5nm厚），栅极材料从四面完全包围每一片纳米片。其关键工艺差异在于：外延生长交替的Si/SiGe超晶格后，选择性去除SiGe层以释放Si纳米片沟道。这一沟道释放步骤在NAND和DRAM中完全没有对应工艺。

未来路线图还包括叉形片晶体管（Forksheet）和互补FET（CFET），后者将NMOS和PMOS垂直堆叠以进一步缩小单元面积。

NAND Flash闪存器件结构：浮栅 → 电荷俘获 → 3D NAND

NAND Flash通过俘获电荷来存储数据，这与逻辑芯片的开关晶体管有本质区别。早期的二维浮栅（Floating Gate）单元使用多晶硅浮栅，隔离在隧穿氧化层（约8nm SiO₂）和多晶硅间介质（ONO叠层：SiO₂/Si₃N₄/SiO₂）之间，上方是控制栅极。电子通过Fowler-Nordheim隧穿进出浮栅，改变单元阈值电压。

电荷俘获闪存（CTF）用Si₃N₄电荷俘获层取代了导电浮栅。由于电荷被束缚在绝缘氮化硅的离散位置而非自由分布在导体上，CTF对相邻单元间干扰的抵抗力更强，这对三维堆叠至关重要。

3D NAND彻底改变了架构方向。制造商不再缩小横向尺寸（二维NAND在约15nm已达物理极限），转而纵向沉积交替的氧化物/氮化物（O/N）层对。当前量产已超过200层，行业目标是到2030年达到1,000层。在整个叠层中刻蚀出垂直沟道孔，内壁依次沉积阻挡氧化层、电荷俘获氮化层、隧穿氧化层，最后填充多晶硅沟道材料。牺牲氮化物层随后在栅极替换工艺中被替换为钨（W）或钼（Mo）字线。